公开(公告)号：US09343552B2

公开(公告)日：2016-05-17

申请号：US14719090

申请日：2015-05-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wan-Te Chen ,  Chung-Hui Chen ,  Jaw-Juinn Horng ,  Po-Zeng Kang

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/93 ,  H01L29/66 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/12 ,  H01L21/8234

CPC classification number: H01L29/6681 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66174 ,  H01L29/7851

Abstract: Embodiments of the present disclosure are a semiconductor device, a FinFET device, and a method of forming a FinFET device. An embodiment is semiconductor device including a first FinFET over a substrate, wherein the first FinFET includes a first set of semiconductor fins. The semiconductor device further includes a first body contact for the first FinFET over the substrate, wherein the first body contact includes a second set of semiconductor fins, and wherein the first body contact is laterally adjacent the first FinFET.

公开(公告)号：US09064725B2

公开(公告)日：2015-06-23

申请号：US13715684

申请日：2012-12-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Wan-Te Chen ,  Chung-Hui Chen ,  Jaw-Juinn Horng ,  Po-Zeng Kang

IPC: H01L29/78 ,  H01L27/088 ,  H01L27/02 ,  H01L27/092 ,  H01L27/12 ,  H01L29/66 ,  H01L27/06

CPC classification number: H01L29/6681 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66174 ,  H01L29/7851

Abstract: Embodiments of the present disclosure are a semiconductor device, a FinFET device, and a method of forming a FinFET device. An embodiment is semiconductor device including a first FinFET over a substrate, wherein the first FinFET includes a first set of semiconductor fins. The semiconductor device further includes a first body contact for the first FinFET over the substrate, wherein the first body contact includes a second set of semiconductor fins, and wherein the first body contact is laterally adjacent the first FinFET.

Abstract translation: 本公开的实施例是半导体器件，FinFET器件和形成FinFET器件的方法。 一个实施例是在衬底上包括第一FinFET的半导体器件，其中第一FinFET包括第一组半导体鳍片。 半导体器件还包括用于衬底上的第一FinFET的第一体接触，其中第一体接触包括第二组半导体鳍片，并且其中第一体接触件与第一FinFET横向相邻。

公开(公告)号：US20140167172A1

公开(公告)日：2014-06-19

申请号：US13715684

申请日：2012-12-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wan-Te Chen ,  Chung-Hui Chen ,  Jaw-Juinn Horng ,  Po-Zeng Kang

IPC: H01L27/04 ,  H01L21/77 ,  H01L27/088

CPC classification number: H01L29/6681 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66174 ,  H01L29/7851

Abstract: Embodiments of the present disclosure are a semiconductor device, a FinFET device, and a method of forming a FinFET device. An embodiment is semiconductor device including a first FinFET over a substrate, wherein the first FinFET includes a first set of semiconductor fins. The semiconductor device further includes a first body contact for the first FinFET over the substrate, wherein the first body contact includes a second set of semiconductor fins, and wherein the first body contact is laterally adjacent the first FinFET.

Abstract translation: 本公开的实施例是半导体器件，FinFET器件和形成FinFET器件的方法。 一个实施例是在衬底上包括第一FinFET的半导体器件，其中第一FinFET包括第一组半导体鳍片。 半导体器件还包括用于衬底上的第一FinFET的第一体接触，其中第一体接触包括第二组半导体鳍片，并且其中第一体接触件与第一FinFET横向相邻。

公开(公告)号：US20250031443A1

公开(公告)日：2025-01-23

申请号：US18785647

申请日：2024-07-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Hui Chen ,  Tzu-Ching Chang ,  Weichih Chen ,  Wan-Te Chen ,  Tsung-Hsin Yu ,  Cheng-Hsiang Hsieh

IPC: H01L27/092 ,  G06F30/327 ,  G06F30/36 ,  G06F30/392 ,  G06F115/06 ,  G06F117/12

Abstract: An integrated circuit (IC) including a plurality of finfet cells designed with digital circuit design rules to provide smaller finfet cells with decreased cell heights, and analog circuit cell structures including first finfet cells of the plurality of finfet cells and including at least one cut metal layer. The smaller finfet cells with decreased cell heights provide a first shorter metal track in one direction and the at least one cut metal layer provides a second shorter metal track in another direction to increase maximum electromigration currents in the integrated circuit.

公开(公告)号：US20240362392A1

公开(公告)日：2024-10-31

申请号：US18769843

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shu-Wei Chung ,  Tung-Heng Hsieh ,  Chung-Hui Chen ,  Chung-Yi Lin

IPC: G06F30/392 ,  G06F30/323 ,  G06F30/398 ,  G06F111/20

CPC classification number: G06F30/392 ,  G06F30/323 ,  G06F30/398 ,  G06F2111/20

Abstract: An analog standard cell is provided. An analog standard cell according to the present disclosure includes a first active region and a second active region extending along a first direction, and a plurality of conductive lines in a first metal layer over the first active region and the second active region. The plurality of conductive lines includes a first conductive line and a second conductive line disposed directly over the first active region, a third conductive line and a fourth conductive line disposed directly over the second active region, a middle conductive line disposed between the second conductive line and the third conductive line, a first power line spaced apart from the middle conductive line by the first conductive line and the second conductive line, and a second power line spaced apart from the middle conductive line by the third conductive line and the fourth conductive line.

公开(公告)号：US12093627B2

公开(公告)日：2024-09-17

申请号：US18053602

申请日：2022-11-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chung-Hui Chen ,  Tzu Ching Chang ,  Wan-Te Chen

IPC: G06F30/392 ,  G03F1/70 ,  G06F30/3953 ,  G06F30/398 ,  H01L23/522

CPC classification number: G06F30/392 ,  G03F1/70 ,  G06F30/3953 ,  G06F30/398 ,  H01L23/5226

Abstract: A method (of forming a semiconductor device) includes: forming an active area structure extending in a first direction; forming gate structures over the active area structure and extending in a second direction substantially perpendicular to the first direction; forming contact-source/drain (CSD) conductors over the active area structure, interleaved with corresponding ones of the gate structures, and extending in the second direction; and forming first conductive segments in a first layer of metallization (M_1st layer) over the active area structure and extending in the first direction, the first conductive segments including a first gate-signal-carrying (GSC) conductor which overlaps the active area structure.

公开(公告)号：US12073165B2

公开(公告)日：2024-08-27

申请号：US17476615

申请日：2021-09-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shu-Wei Chung ,  Tung-Heng Hsieh ,  Chung-Hui Chen ,  Chung-Yi Lin

IPC: G06F30/30 ,  G06F30/323 ,  G06F30/392 ,  G06F30/398 ,  G06F111/20

CPC classification number: G06F30/392 ,  G06F30/323 ,  G06F30/398 ,  G06F2111/20

Abstract: An analog standard cell is provided. An analog standard cell according to the present disclosure includes a first active region and a second active region extending along a first direction, and a plurality of conductive lines in a first metal layer over the first active region and the second active region. The plurality of conductive lines includes a first conductive line and a second conductive line disposed directly over the first active region, a third conductive line and a fourth conductive line disposed directly over the second active region, a middle conductive line disposed between the second conductive line and the third conductive line, a first power line spaced apart from the middle conductive line by the first conductive line and the second conductive line, and a second power line spaced apart from the middle conductive line by the third conductive line and the fourth conductive line.

公开(公告)号：US11984444B2

公开(公告)日：2024-05-14

申请号：US17357818

申请日：2021-06-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chung-Hui Chen ,  Wan-Te Chen ,  Tzu Ching Chang ,  Tsung-Hsin Yu

IPC: H01L27/06 ,  H01L21/8234 ,  H01L23/522

CPC classification number: H01L27/0629 ,  H01L21/823475 ,  H01L23/5222

Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a first active region extending along a first direction. The semiconductor device also includes a second active region extending along the first direction. The semiconductor device further includes a first gate extending along a second direction perpendicular to the first direction. The first gate has a first segment disposed between the first active region and the second active region. In addition, the semiconductor device includes a first electrical conductor extending along the second direction and across the first active region and the second active region, wherein the first segment of the first gate and the first electrical conductor are partially overlapped to form a first capacitor.

公开(公告)号：US20230387331A1

公开(公告)日：2023-11-30

申请号：US18358464

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Hui Chen

IPC: H01L29/94 ,  H01L21/762 ,  H01L27/06 ,  H01L27/08 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/945 ,  H01L21/76224 ,  H01L28/92 ,  H01L27/0629 ,  H01L27/0811 ,  H01L29/4236 ,  H01L29/94 ,  H01L27/0805 ,  H01L29/66181 ,  H01L27/1211

Abstract: A semiconductor device including field-effect transistors (finFETs) and fin capacitors are formed on a silicon substrate. The fin capacitors include silicon fins, one or more electrical conductors between the silicon fins, and insulating material between the silicon fins and the one or more electrical conductors. The fin capacitors may also include insulating material between the one or more electrical conductors and underlying semiconductor material.

公开(公告)号：US10522637B2

公开(公告)日：2019-12-31

申请号：US16401335

申请日：2019-05-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chung-Hui Chen

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L27/088 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/02

Abstract: A semiconductor structure includes a first GAA transistor and a second GAA transistor. The first GAA transistor includes: a first diffusion region, a second diffusion region, and a first nanowire. The second GAA transistor includes: a third diffusion region, a fourth diffusion region, and a second nanowire. The first diffusion region, the second diffusion region, and the first nanowire are symmetrical with the third diffusion region, the fourth diffusion region, and the second nanowire respectively, the first GAA transistor is arranged to provide a first current to flow through the first nanowire, and the second GAA transistor is arranged to provide a second current to flow through the second nanowire.