SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME

    公开(公告)号:US20230337415A1

    公开(公告)日:2023-10-19

    申请号:US18337134

    申请日:2023-06-19

    CPC classification number: H10B12/34 H10B12/053 H10B12/315 H10B12/0335

    Abstract: Disclosed are a semiconductor memory device and a method of fabricating the same. The device includes a substrate including an active pattern with doped regions, a gate electrode crossing the active pattern between the doped regions, a bit line crossing the active pattern and being electrically connected to one of the doped regions, a spacer on a side surface of the bit line, a first contact coupled to another of the doped regions and spaced apart from the bit line with the spacer interposed therebetween, a landing pad on the first contact, and a data storing element on the landing pad. The another of the doped regions has a top surface, an upper side surface, and a curved top surface that extends from the top surface to the upper side surface. The first contact is in contact with the curved top surface and the upper side surface.

    Variable resistance memory device
    45.
    发明授权

    公开(公告)号:US11538861B2

    公开(公告)日:2022-12-27

    申请号:US17167851

    申请日:2021-02-04

    Abstract: Disclosed is a variable resistance memory device including a first conductive line extending in a first direction parallel to a top surface of the substrate, memory cells spaced apart from each other in the first direction on a side of the first conductive line and connected to the first conductive line, and second conductive lines respectively connected to the memory cells. Each second conductive line is spaced apart in a second direction from the first conductive line. The second direction is parallel to the top surface of the substrate and intersects the first direction. The second conductive lines extend in a third direction perpendicular to the top surface of the substrate and are spaced apart from each other in the first direction. Each memory cell includes a variable resistance element and a select element that are positioned at a same level horizontally arranged in the second direction.

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

    公开(公告)号:US20210351184A1

    公开(公告)日:2021-11-11

    申请号:US17384347

    申请日:2021-07-23

    Abstract: A semiconductor device includes: an active region defined by a device isolation layer formed in a substrate; a word line configured to cross the active region, the word line extending in a first direction and being formed in the substrate; a bit line extending in a second direction perpendicular to the first direction on the word line; a first contact connecting the bit line to the active region; a first mask for forming the active region, the first mask being formed on the active region; and a second mask of which a height of a top surface thereof is greater than a height of a top surface of the active region, the second mask covering the word line, wherein the active region has a bar shape that extends to form an acute angle with respect to the first direction.

    SEMICONDUCTOR MEMORY DEVICE
    47.
    发明申请

    公开(公告)号:US20210210432A1

    公开(公告)日:2021-07-08

    申请号:US17205462

    申请日:2021-03-18

    Abstract: A semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate, bit line structures crossing over the word lines and extending in a second direction intersecting the first direction, and contact pad structures between the word lines and between the bit line structures in plan view. A spacer structure extends between the bit line structures and the contact pad structures. The spacer structure includes a first air gap extending in the second direction along sidewalls of the bit line structures and a second air gap surrounding each of the contact pad structures and coupled to the first air gap.

    Variable resistance memory device
    48.
    发明授权

    公开(公告)号:US10937833B2

    公开(公告)日:2021-03-02

    申请号:US16455791

    申请日:2019-06-28

    Abstract: Disclosed is a variable resistance memory device including a first conductive line extending in a first direction parallel to a top surface of the substrate, memory cells spaced apart from each other in the first direction on a side of the first conductive line and connected to the first conductive line, and second conductive lines respectively connected to the memory cells. Each second conductive line is spaced apart in a second direction from the first conductive line. The second direction is parallel to the top surface of the substrate and intersects the first direction. The second conductive lines extend in a third direction perpendicular to the top surface of the substrate and are spaced apart from each other in the first direction. Each memory cell includes a variable resistance element and a select element that are positioned at a same level horizontally arranged in the second direction.

    SEMICONDUCTOR DEVICE
    50.
    发明公开

    公开(公告)号:US20240244832A1

    公开(公告)日:2024-07-18

    申请号:US18378191

    申请日:2023-10-10

    CPC classification number: H10B12/488 H10B12/482 H10B12/485

    Abstract: A semiconductor device including: a device isolation part on a substrate to define first to fourth active regions, the device isolation part interposed between the first and second active regions and the third and fourth active regions; first and second word lines crossing the first and second active regions and adjacent to each other; a first impurity region in the first active region between the first and second word lines; a second impurity region in the first active region at one side of the first word line and spaced apart from the first impurity region; a first conductive pad contacting the first impurity region; a second conductive pad contacting the second impurity region; a bit line on the first conductive pad; a storage node contact on the second conductive pad; and a landing pad on the storage node contact.

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