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公开(公告)号:US20230337415A1
公开(公告)日:2023-10-19
申请号:US18337134
申请日:2023-06-19
Applicant: Samsung Electronics Co., Ltd.
Inventor: Minsu Choi , Myeong-Dong Lee , Hyeon-Woo Jang , Keunnam Kim , Sooho Shin , Yoosang Hwang
IPC: H10B12/00
CPC classification number: H10B12/34 , H10B12/053 , H10B12/315 , H10B12/0335
Abstract: Disclosed are a semiconductor memory device and a method of fabricating the same. The device includes a substrate including an active pattern with doped regions, a gate electrode crossing the active pattern between the doped regions, a bit line crossing the active pattern and being electrically connected to one of the doped regions, a spacer on a side surface of the bit line, a first contact coupled to another of the doped regions and spaced apart from the bit line with the spacer interposed therebetween, a landing pad on the first contact, and a data storing element on the landing pad. The another of the doped regions has a top surface, an upper side surface, and a curved top surface that extends from the top surface to the upper side surface. The first contact is in contact with the curved top surface and the upper side surface.
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公开(公告)号:US11776909B2
公开(公告)日:2023-10-03
申请号:US17205462
申请日:2021-03-18
Applicant: Samsung Electronics Co., Ltd.
Inventor: Eunjung Kim , Hui-Jung Kim , Keunnam Kim , Daeik Kim , Bong-soo Kim , Yoosang Hwang
IPC: H01L21/764 , H01L23/532 , H10B12/00 , H01L23/522 , H01L23/528 , H10B63/00
CPC classification number: H01L23/5329 , H01L21/764 , H01L23/5226 , H01L23/5283 , H10B12/0335 , H01L23/5222 , H10B12/315 , H10B63/30 , H10B63/80
Abstract: A semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate, bit line structures crossing over the word lines and extending in a second direction intersecting the first direction, and contact pad structures between the word lines and between the bit line structures in plan view. A spacer structure extends between the bit line structures and the contact pad structures. The spacer structure includes a first air gap extending in the second direction along sidewalls of the bit line structures and a second air gap surrounding each of the contact pad structures and coupled to the first air gap.
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公开(公告)号:US11728167B2
公开(公告)日:2023-08-15
申请号:US17680996
申请日:2022-02-25
Applicant: Samsung Electronics Co., Ltd.
Inventor: Dongjun Lee , Keunnam Kim , Daehyoun Kim , Taejin Park , Sunghee Han
IPC: H01L21/033 , H01L21/027 , H01L21/768 , H01L21/311
CPC classification number: H01L21/0337 , H01L21/0273 , H01L21/31144 , H01L21/76816
Abstract: A hardmask structure including a plurality of hardmask layers is formed on a target layer in a first area and a second area, a first photoresist pattern in the first area and a second photoresist pattern in the second area are formed, a reversible hardmask pattern including a plurality of openings is formed by transferring shapes of the first and second photoresist patterns to a reversible hardmask layer that is one of the plurality of hardmask layers, a gap-fill hardmask pattern is formed by filling some of the plurality of openings formed in the first area with a gap-fill hardmask pattern material, and a feature pattern is formed in the target layer by transferring a shape of the gap-fill hardmask pattern to the target layer in the first area and a shape of the reversible hardmask pattern to the target layer in the second area.
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公开(公告)号:US20230180468A1
公开(公告)日:2023-06-08
申请号:US18052689
申请日:2022-11-04
Applicant: Samsung Electronics Co., Ltd.
Inventor: Kiseok Lee , Moonyoung Jeong , Jong-Ho Moon , Han-Sik Yoo , Keunnam Kim , Hyungeun Choi
IPC: H01L27/108 , H01L25/065 , H01L25/18 , H01L23/00 , H01L25/00
CPC classification number: H01L27/10897 , H01L24/06 , H01L24/08 , H01L24/80 , H01L25/18 , H01L25/50 , H01L25/0657 , H01L27/10805 , H01L27/10894 , H01L2224/06515 , H01L2224/08145 , H01L2224/80006 , H01L2224/80895 , H01L2224/80896 , H01L2924/1431 , H01L2924/1436
Abstract: A semiconductor memory device may include a cell array structure including first bonding pads, which are electrically connected to memory cells, and a peripheral circuit structure including second bonding pads, which are electrically connected to peripheral circuits and are bonded to the first bonding pads. The cell array structure may include a stack including horizontal conductive patterns stacked in a vertical direction, a vertical structure including vertical conductive patterns , which are provided to cross the stack in the vertical direction, and a power capacitor provided in a planarization insulating layer covering a portion of the stack.
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公开(公告)号:US11538861B2
公开(公告)日:2022-12-27
申请号:US17167851
申请日:2021-02-04
Applicant: Samsung Electronics Co., Ltd.
Inventor: Hui-Jung Kim , Kiseok Lee , Keunnam Kim , Yoosang Hwang
Abstract: Disclosed is a variable resistance memory device including a first conductive line extending in a first direction parallel to a top surface of the substrate, memory cells spaced apart from each other in the first direction on a side of the first conductive line and connected to the first conductive line, and second conductive lines respectively connected to the memory cells. Each second conductive line is spaced apart in a second direction from the first conductive line. The second direction is parallel to the top surface of the substrate and intersects the first direction. The second conductive lines extend in a third direction perpendicular to the top surface of the substrate and are spaced apart from each other in the first direction. Each memory cell includes a variable resistance element and a select element that are positioned at a same level horizontally arranged in the second direction.
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公开(公告)号:US20210351184A1
公开(公告)日:2021-11-11
申请号:US17384347
申请日:2021-07-23
Applicant: Samsung Electronics Co., Ltd.
Inventor: Hyosub Kim , Keunnam Kim , Dongoh Kim , Bongsoo Kim , Euna Kim , Chansic Yoon , Kiseok Lee , Hyeonok Jung , Sunghee Han , Yoosang Hwang
IPC: H01L27/108 , H01L23/528
Abstract: A semiconductor device includes: an active region defined by a device isolation layer formed in a substrate; a word line configured to cross the active region, the word line extending in a first direction and being formed in the substrate; a bit line extending in a second direction perpendicular to the first direction on the word line; a first contact connecting the bit line to the active region; a first mask for forming the active region, the first mask being formed on the active region; and a second mask of which a height of a top surface thereof is greater than a height of a top surface of the active region, the second mask covering the word line, wherein the active region has a bar shape that extends to form an acute angle with respect to the first direction.
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公开(公告)号:US20210210432A1
公开(公告)日:2021-07-08
申请号:US17205462
申请日:2021-03-18
Applicant: Samsung Electronics Co., Ltd.
Inventor: Eunjung Kim , Hui-Jung Kim , Keunnam Kim , Daeik Kim , Bong-soo Kim , Yoosang Hwang
IPC: H01L23/532 , H01L21/764 , H01L27/108 , H01L23/522 , H01L23/528
Abstract: A semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate, bit line structures crossing over the word lines and extending in a second direction intersecting the first direction, and contact pad structures between the word lines and between the bit line structures in plan view. A spacer structure extends between the bit line structures and the contact pad structures. The spacer structure includes a first air gap extending in the second direction along sidewalls of the bit line structures and a second air gap surrounding each of the contact pad structures and coupled to the first air gap.
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公开(公告)号:US10937833B2
公开(公告)日:2021-03-02
申请号:US16455791
申请日:2019-06-28
Applicant: Samsung Electronics Co., Ltd.
Inventor: Hui-Jung Kim , Kiseok Lee , Keunnam Kim , Yoosang Hwang
Abstract: Disclosed is a variable resistance memory device including a first conductive line extending in a first direction parallel to a top surface of the substrate, memory cells spaced apart from each other in the first direction on a side of the first conductive line and connected to the first conductive line, and second conductive lines respectively connected to the memory cells. Each second conductive line is spaced apart in a second direction from the first conductive line. The second direction is parallel to the top surface of the substrate and intersects the first direction. The second conductive lines extend in a third direction perpendicular to the top surface of the substrate and are spaced apart from each other in the first direction. Each memory cell includes a variable resistance element and a select element that are positioned at a same level horizontally arranged in the second direction.
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公开(公告)号:US09960170B1
公开(公告)日:2018-05-01
申请号:US15614077
申请日:2017-06-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Daeik Kim , Kiseok Lee , Keunnam Kim , Bong-Soo Kim , Jemin Park , Chan-Sic Yoon , Yoosang Hwang
IPC: H01L21/8242 , H01L27/108
CPC classification number: H01L27/10897 , H01L27/10814 , H01L27/10823 , H01L27/10852 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L27/10894
Abstract: Methods of fabricating a memory device are provided. The methods may include forming a mask pattern including line-shaped portions that are parallel to each other and extend on a first region of a substrate. The mask pattern may extend on a second region of the substrate. The methods may also include forming word line regions in the first region using the mask pattern as a mask, forming word lines in the word line regions, respectively, and removing the mask pattern from the second region to expose the second region. The mask pattern may remain on the first region after removing the mask pattern from the second region. The methods may further include forming a channel epitaxial layer on the second region while using the mask pattern as a barrier to growth of the channel epitaxial layer on the first region.
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公开(公告)号:US20240244832A1
公开(公告)日:2024-07-18
申请号:US18378191
申请日:2023-10-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Kiseok Lee , Keunnam Kim , Hui-Jung Kim
IPC: H10B12/00
CPC classification number: H10B12/488 , H10B12/482 , H10B12/485
Abstract: A semiconductor device including: a device isolation part on a substrate to define first to fourth active regions, the device isolation part interposed between the first and second active regions and the third and fourth active regions; first and second word lines crossing the first and second active regions and adjacent to each other; a first impurity region in the first active region between the first and second word lines; a second impurity region in the first active region at one side of the first word line and spaced apart from the first impurity region; a first conductive pad contacting the first impurity region; a second conductive pad contacting the second impurity region; a bit line on the first conductive pad; a storage node contact on the second conductive pad; and a landing pad on the storage node contact.
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