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公开(公告)号：US11410951B2
公开(公告)日：2022-08-09
申请号：US17207242
申请日：2021-03-19
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hyungeun Choi , Eun-Ji Kim , Jong-Ho Moon , Hyoungyol Mun , Han-Sik Yoo , Kiseok Lee , Seungjae Jung , Taehyun An , Sangyeon Han , Yoosang Hwang
IPC: H01L27/108 , G11C11/408 , H01L25/065 , G11C11/4091 , H01L23/00 , H01L25/18
Abstract: A three-dimensional semiconductor memory device is provided. The device may include a first substrate including a bit-line connection region and a word-line connection region, a cell array structure on the first substrate, a second substrate including a first core region and a second core region, which are respectively overlapped with the bit-line connection region and the word-line connection region, and a peripheral circuit structure on the second substrate.
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Patent Agency Ranking
公开(公告)号：US20230180468A1
公开(公告)日：2023-06-08
申请号：US18052689
申请日：2022-11-04
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kiseok Lee , Moonyoung Jeong , Jong-Ho Moon , Han-Sik Yoo , Keunnam Kim , Hyungeun Choi
IPC: H01L27/108 , H01L25/065 , H01L25/18 , H01L23/00 , H01L25/00
CPC classification number: H01L27/10897 , H01L24/06 , H01L24/08 , H01L24/80 , H01L25/18 , H01L25/50 , H01L25/0657 , H01L27/10805 , H01L27/10894 , H01L2224/06515 , H01L2224/08145 , H01L2224/80006 , H01L2224/80895 , H01L2224/80896 , H01L2924/1431 , H01L2924/1436
Abstract: A semiconductor memory device may include a cell array structure including first bonding pads, which are electrically connected to memory cells, and a peripheral circuit structure including second bonding pads, which are electrically connected to peripheral circuits and are bonded to the first bonding pads. The cell array structure may include a stack including horizontal conductive patterns stacked in a vertical direction, a vertical structure including vertical conductive patterns , which are provided to cross the stack in the vertical direction, and a power capacitor provided in a planarization insulating layer covering a portion of the stack.
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公开(公告)号：US20130256832A1
公开(公告)日：2013-10-03
申请号：US13792867
申请日：2013-03-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Han-Sik Yoo , Se-Il Oh
CPC classification number: H01L27/0805 , H01L27/04 , H01L28/90
Abstract: A semiconductor device includes an internal circuit and a cell-type power decoupling capacitor. The cell-type power decoupling capacitor is formed on a semiconductor substrate using a stack cell capacitor process. The cell-type power decoupling capacitor stabilizes a supply voltage to provide the stabilized supply voltage to the internal circuit. Accordingly, the semiconductor device including the cell-type power decoupling capacitor may be insensitive to power noise and may occupy a small area on a chip.
Abstract translation: 半导体器件包括内部电路和电池型功率去耦电容器。 电池型功率去耦电容器使用堆叠电池电容器工艺形成在半导体衬底上。 电池型功率去耦电容稳定电源电压，以向内部电路提供稳定的电源电压。 因此，包括单元型功率去耦电容器的半导体器件可能对功率噪声不敏感，并且可能占用芯片上的小面积。
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公开(公告)号：US20220068859A1
公开(公告)日：2022-03-03
申请号：US17207242
申请日：2021-03-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyungeun Choi , Eun-Ji Kim , Jong-Ho Moon , Hyoungyol Mun , Han-Sik Yoo , Kiseok Lee , Seungjae Jung , Taehyun An , Sangyeon Han , Yoosang Hwang
IPC: H01L23/00 , H01L27/108 , G11C11/408 , G11C11/4091 , H01L25/065 , H01L25/18
Abstract: A three-dimensional semiconductor memory device is provided. The device may include a first substrate including a bit-line connection region and a word-line connection region, a cell array structure on the first substrate, a second substrate including a first core region and a second core region, which are respectively overlapped with the bit-line connection region and the word-line connection region, and a peripheral circuit structure on the second substrate.
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公开(公告)号：US09806080B2
公开(公告)日：2017-10-31
申请号：US14731764
申请日：2015-06-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Han-Sik Yoo , Hyuk-Joon Kwon , Jung-Ha Oh , Jun-Ho Kim
IPC: H01L27/108 , H01L29/94 , G11C11/56 , G11C29/52 , H01L23/528 , H01L49/02 , G11C16/04 , G06F11/10 , G11C29/42 , G11C29/04 , H01L27/11582
CPC classification number: H01L27/10823 , G06F11/1048 , G11C11/5635 , G11C11/5671 , G11C16/0466 , G11C29/42 , G11C29/52 , G11C2029/0411 , H01L23/528 , H01L27/10814 , H01L27/11582 , H01L28/40 , H01L2924/0002 , H01L2924/00
Abstract: A semiconductor device includes a substrate, a memory structure and a capacitor structure including at least one array of capacitors. The memory structure is disposed in a first region of the device. The capacitor structure is disposed in a second region of the device. The capacitor structure may include a first capacitor array, a second capacitor array, a third capacitor array and a first landing pad. The first landing pad is disposed between the substrate and lower electrodes of capacitors of the first and second capacitor arrays, and contacts the lower electrodes so as to electrically connect the first capacitor array and the second capacitor array. Upper electrodes of capacitors of the second and third capacitor arrays are integral such that the second capacitor array and the third capacitor array are electrically connected to each other.
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公开(公告)号：US09305919B2
公开(公告)日：2016-04-05
申请号：US13792867
申请日：2013-03-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Han-Sik Yoo , Se-Il Oh
CPC classification number: H01L27/0805 , H01L27/04 , H01L28/90
Abstract: A semiconductor device includes an internal circuit and a cell-type power decoupling capacitor. The cell-type power decoupling capacitor is formed on a semiconductor substrate using a stack cell capacitor process. The cell-type power decoupling capacitor stabilizes a supply voltage to provide the stabilized supply voltage to the internal circuit. Accordingly, the semiconductor device including the cell-type power decoupling capacitor may be insensitive to power noise and may occupy a small area on a chip.
Abstract translation: 半导体器件包括内部电路和电池型功率去耦电容器。 电池型功率去耦电容器使用堆叠电池电容器工艺形成在半导体衬底上。 电池型功率去耦电容稳定电源电压，以向内部电路提供稳定的电源电压。 因此，包括单元型功率去耦电容器的半导体器件可能对功率噪声不敏感，并且可能占用芯片上的小面积。
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