公开(公告)号：US20140293680A1

公开(公告)日：2014-10-02

申请号：US14263307

申请日：2014-04-28

Applicant: Renesas Electronics Corporation

Inventor： Koji NII ,  Shigeki OHBAYASHI ,  Yasumasa TSUKAMOTO ,  Makoto YABUUCHI

IPC: G11C11/417 ,  G11C5/14 ,  G11C5/06

CPC classification number: G11C11/419 ,  G11C5/06 ,  G11C5/14 ,  G11C8/08 ,  G11C11/417 ,  G11C11/418

Abstract: In a semiconductor memory device, static memory cells are arranged in rows and columns, word lines correspond to respective memory cell rows, and word line drivers drive correspond to word lines. Cell power supply lines correspond to respective memory cell columns and are coupled to cell power supply nodes of a memory cell in a corresponding column. Down power supply lines are arranged corresponding to respective memory cell columns, maintained at ground voltage in data reading and rendered electrically floating in data writing. Write assist elements are arranged corresponding to the cell power supply lines, and according to a write column instruction signal for stopping supply of a cell power supply voltage to the cell power supply line in a selected column, and for coupling the cell power supply line arranged corresponding to the selected column at least to the down power supply line on the corresponding column.

Abstract translation: 在半导体存储器件中，静态存储单元以行和列排列，字线对应于相应的存储单元行，并且字线驱动器对应于字线。 单元电源线对应于相应的存储单元列并且耦合到相应列中的存储器单元的单元电源节点。 向下电源线被布置成对应于相应的存储单元列，保持在数据读取中的接地电压并且在数据写入中被电浮动。 写入辅助元件对应于单电池电源线布置，并且根据写入列指示信号，用于停止向所选列中的单元电源线提供单元电源电压，并且用于耦合布置的单元电源线 对应于所选列至少至相应列上的下电源线。

公开(公告)号：US20210142849A1

公开(公告)日：2021-05-13

申请号：US17095000

申请日：2020-11-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Makoto YABUUCHI

IPC: G11C11/418

Abstract: Along with the miniaturization of the semiconductor memory device, the resistor and parasitic capacitance of the wires become large, which prevents the semiconductor memory device from being speeded up. In a semiconductor memory device having a semiconductor substrate having a main surface, a first memory cell row having a plurality of first memory cells arranged in parallel to a first direction in plan view on the main surface, a first word line connected to the plurality of first memory cells, a first word line driver for changing a potential of the first word line, and a control circuit for outputting a first predecode signal to the first word line driver via the first predecode line in response to a clock signal and an address signal, a repeater is inserted between the control circuit and the first word line driver.

公开(公告)号：US20190198499A1

公开(公告)日：2019-06-27

申请号：US16287570

申请日：2019-02-27

Applicant: Renesas Electronics Corporation

Inventor： Makoto YABUUCHI ,  Yuichiro Ishii

IPC: H01L27/092 ,  H01L21/8238 ,  H01L23/528

CPC classification number: H01L27/0924 ,  H01L21/823475 ,  H01L21/823493 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823892 ,  H01L23/528 ,  H01L23/5286 ,  H01L27/0928

Abstract: A semiconductor device includes a semiconductor substrate, a first well region formed on the semiconductor substrate, a first fin integrally formed of the semiconductor substrate on the first well region and extended in a first direction in a plan view, a first electrode formed on the first fin via a first gate insulating film, and extended in a second direction crossing the first direction in the plan view, a tap region formed on the semiconductor substrate adjacent to the first well region in the second direction, and supplying a first potential to the first well region, a second fin integrally formed of the semiconductor substrate on the tap region and extended in the first direction in the plan view, and a first wiring layer formed on the second fin in a portion overlapping the tap region in the plan view.

公开(公告)号：US20180261280A1

公开(公告)日：2018-09-13

申请号：US15981355

申请日：2018-05-16

Applicant: Renesas Electronics Corporation

Inventor： Shinji TANAKA ,  Makoto YABUUCHI ,  Yuta YOSHIDA

IPC: G11C11/419 ,  G11C8/08 ,  G11C8/10 ,  G11C11/415 ,  G11C7/08 ,  G11C11/418 ,  G11C5/06 ,  G11C7/22

CPC classification number: G11C11/419 ,  G11C5/06 ,  G11C5/063 ,  G11C7/08 ,  G11C7/227 ,  G11C8/08 ,  G11C8/10 ,  G11C11/415 ,  G11C11/418

Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.

公开(公告)号：US20180211956A1

公开(公告)日：2018-07-26

申请号：US15925762

申请日：2018-03-19

Applicant: Renesas Electronics Corporation

Inventor： Makoto YABUUCHI

IPC: H01L27/088 ,  H01L27/06 ,  H01L27/02 ,  G11C7/10

CPC classification number: H01L27/0886 ,  G11C7/10 ,  G11C7/1084 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/0924

Abstract: Data hold time is controlled without excessively increasing a circuit area. A semiconductor device includes a data buffer and a flip-flop formed of fin. As a delay line, gate wirings being in the same layer as gate electrodes of the fin are provided in a data signal path from a data output node of the data buffer to a data input node of the flip-flop.

公开(公告)号：US20180158522A1

公开(公告)日：2018-06-07

申请号：US15885449

申请日：2018-01-31

Applicant: Renesas Electronics Corporation

Inventor： Yuichiro ISHII ,  Makoto YABUUCHI ,  Masao MORIMOTO

IPC: G11C11/419 ,  G11C11/418 ,  G11C8/16 ,  G11C8/18 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C8/00

CPC classification number: G11C11/419 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C7/222 ,  G11C8/00 ,  G11C8/06 ,  G11C8/08 ,  G11C8/16 ,  G11C8/18 ,  G11C11/418

Abstract: A circuit includes a memory cell array which includes: a plurality of memory cells; a plurality of word lines coupled to the memory cells, respectively, and a plurality of bit lines coupled to the memory cells, an address control circuit which includes: a first latch circuit into which a first address signal is input and from which a first output signal is output; a selection circuit into which a second address signal and the first output signal are input and which selects the first output signal or the second address signal for outputting the first output signal or the second address signal as a second output signal; a second latch circuit into which the second output signal is input and from which a third output signal is output; a decode circuit which decodes the third output signal and outputs a fourth output signal; and a word line drive circuit.

公开(公告)号：US20170236579A1

公开(公告)日：2017-08-17

申请号：US15586870

申请日：2017-05-04

Applicant: Renesas Electronics Corporation

Inventor： Koji NII ,  Shigeki OHBAYASHI ,  Yasumasa TSUKAMOTO ,  Makoto YABUUCHI

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C5/06 ,  G11C5/14 ,  G11C8/08 ,  G11C11/4085 ,  G11C11/417

Abstract: In a semiconductor memory device, static memory cells are arranged in rows and columns, word lines correspond to respective memory cell rows, and word line drivers drive correspond to word lines. Cell power supply lines correspond to respective memory cell columns and are coupled to cell power supply nodes of a memory cell in a corresponding column. Down power supply lines are arranged corresponding to respective memory cell columns, maintained at ground voltage in data reading and rendered electrically floating in data writing. Write assist elements are arranged corresponding to the cell power supply lines, and according to a write column instruction signal for stopping supply of a cell power supply voltage to the cell power supply line in a selected column, and for coupling the cell power supply line arranged corresponding to the selected column at least to the down power supply line on the corresponding column.

公开(公告)号：US20170047129A1

公开(公告)日：2017-02-16

申请号：US15337139

申请日：2016-10-28

Applicant: Renesas Electronics Corporation

Inventor： Makoto YABUUCHI

IPC: G11C29/12 ,  H01L27/11 ,  G11C7/12 ,  G11C8/08 ,  G11C7/22

CPC classification number: G11C29/1201 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C8/08 ,  G11C11/412 ,  G11C11/419 ,  G11C29/12015 ,  G11C2029/1202 ,  G11C2029/1204 ,  H01L27/1104 ,  H01L27/1116

Abstract: Provided is a semiconductor storage device including: first memory cells; first word lines; first bit lines; a first common bit line; second memory cells; second word lines; second bit lines; a second common bit line; a first selection circuit that connects the first common bit line to a first bit line selected from the first bit lines; a second selection circuit that connects the second common bit line to a second bit line selected from the second bit lines; a word line driver that activates any one of the first and second word lines; a reference current supply unit that supplies a reference current to a common bit line among the first and second common bit lines, the common bit line not being electrically connected to a data read target memory cell; and a sense amplifier that amplifies a potential difference between the first and second common bit lines.

Abstract translation: 提供一种半导体存储装置，包括：第一存储单元; 第一个字线 第一位线 第一个通用位线; 第二存储单元; 第二个字线 第二位线 第二个通用位线; 第一选择电路，其将第一公共位线连接到从第一位线选择的第一位线; 第二选择电路，其将所述第二公共位线连接到从所述第二位线选择的第二位线; 字线驱动器，其激活第一和第二字线中的任何一个; 参考电流供应单元，其将第一和第二公共位线之间的公共位线提供参考电流，所述公共位线不电连接到数据读取目标存储器单元; 以及放大第一和第二公共位线之间的电位差的读出放大器。

公开(公告)号：US20160358667A1

公开(公告)日：2016-12-08

申请号：US15240863

申请日：2016-08-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hidehiro FUJIWARA ,  Makoto YABUUCHI ,  Koji NII ,  Yoshikazu SAITO

IPC: G11C29/12 ,  G11C11/417

CPC classification number: G11C29/44 ,  G06K19/0722 ,  G11C7/10 ,  G11C11/417 ,  G11C29/06 ,  G11C29/12 ,  G11C2029/4402

Abstract: A semiconductor device having a capability of generating chip identification information includes: an SRAM macro having a plurality of memory cells arranged in rows and columns: a test address storage unit configured to store a test address; a self-diagnostic circuit configured to output the test address based on a result of confirmation of operation of the memory cell selected by the test address; and an identification information generation circuit configured to generate chip identification information based on the test address which is output by the self-diagnostic circuit.

Abstract translation: 具有产生芯片识别信息的能力的半导体器件包括：具有以行和列排列的多个存储单元的SRAM宏;测试地址存储单元，被配置为存储测试地址; 自诊断电路，被配置为基于由测试地址选择的存储器单元的操作的确认结果来输出测试地址; 以及识别信息生成电路，被配置为基于由所述自诊断电路输出的测试地址来生成芯片识别信息。

公开(公告)号：US20160358645A1

公开(公告)日：2016-12-08

申请号：US15239410

申请日：2016-08-17

Applicant: Renesas Electronics Corporation

Inventor： Makoto YABUUCHI ,  Hidehiro FUJIWARA

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C11/417 ,  G11C11/418 ,  G11C17/12

Abstract: There is provided a semiconductor integrated circuit device that can generate a unique ID with the suppression of overhead. When a unique ID is generated, the potential of a word line of a memory cell in an SRAM is raised above the power supply voltage of the SRAM, and then lowered below the power supply voltage of the SRAM. When the potential of the word line is above the power supply voltage of the SRAM, the same data is supplied to both the bit lines of the memory cell. Thereby, the memory cell in the SRAM is put into an undefined state and then changed so as to hold data according to characteristics of elements or the like configuring the memory cell. In the manufacture of the SRAM, there occur variations in characteristics of elements or the like configuring the memory cell. Accordingly, the memory cell in the SRAM holds data according to variations occurring in the manufacture.