公开(公告)号：US20180261720A1

公开(公告)日：2018-09-13

申请号：US15980583

申请日：2018-05-15

Applicant: Applied Materials, Inc.

Inventor： Mingwei ZHU ,  Nag B. PATIBANDLA ,  Rongjun WANG ,  Daniel Lee DIEHL ,  Vivek AGRAWAL ,  Anantha Subramani

IPC: H01L33/12 ,  H01L29/20 ,  H01L33/00 ,  H01J37/34 ,  H01J37/32 ,  H01L31/18

CPC classification number: H01L33/12 ,  H01J37/32467 ,  H01J37/32724 ,  H01J37/3405 ,  H01J37/347 ,  H01L29/2003 ,  H01L31/1856 ,  H01L33/007 ,  H01L33/0075 ,  Y02E10/544

Abstract: Oxygen controlled PVD AlN buffers for GaN-based optoelectronic and electronic devices is described. Methods of forming a PVD AlN buffer for GaN-based optoelectronic and electronic devices in an oxygen controlled manner are also described. In an example, a method of forming an aluminum nitride (AlN) buffer layer for GaN-based optoelectronic or electronic devices involves reactive sputtering an AlN layer above a substrate, the reactive sputtering involving reacting an aluminum-containing target housed in a physical vapor deposition (PVD) chamber with a nitrogen-containing gas or a plasma based on a nitrogen-containing gas. The method further involves incorporating oxygen into the AlN layer.

公开(公告)号：US20170170393A1

公开(公告)日：2017-06-15

申请号：US15438420

申请日：2017-02-21

Applicant: Applied Materials, Inc.

Inventor： Lin XUE ,  Jaesoo AHN ,  Mahendra PAKALA ,  Chi Hong CHING ,  Rongjun WANG

IPC: H01L43/12 ,  H01F10/32 ,  H01F10/14 ,  H01L43/08 ,  H01L43/10

CPC classification number: H01L43/12 ,  H01F10/14 ,  H01F10/3222 ,  H01L43/08 ,  H01L43/10

Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate in for spin-transfer-torque magnetoresistive random access memory (STT-MRAM) applications. In one example, a film stack utilized to form a magnetic tunnel junction structure on a substrate includes a pinned layer disposed on a substrate, wherein the pinned layer comprises multiple layers including at least one or more of a Co containing layer, Pt containing layer, Ta containing layer, an Ru containing layer, an optional structure decoupling layer disposed on the pinned magnetic layer, a magnetic reference layer disposed on the optional structure decoupling layer, a tunneling barrier layer disposed on the magnetic reference layer, a magnetic storage layer disposed on the tunneling barrier layer, and a capping layer disposed on the magnetic storage layer.

公开(公告)号：US20240371771A1

公开(公告)日：2024-11-07

申请号：US18423437

申请日：2024-01-26

Applicant: Applied Materials, Inc.

Inventor： Sahil Jaykumar PATEL ,  Wei LEI ,  Tuerxun AILIHUMAER ,  Joung Joo LEE ,  Rongjun WANG ,  Xianmin TANG

IPC: H01L23/532 ,  H01L21/768

Abstract: Embodiments of the disclosure include an apparatus and method of forming a semiconductor structure that includes metal contacts with a low resistance. In some embodiments, the semiconductor device generally includes an interconnect. The interconnect generally includes a dielectric layer with a tungsten (W) plug formed therein, a feature formed in the dielectric layer and over the W plug, a liner layer formed on an exposed surface of the W plug and on sidewalls of the feature, an interruption layer formed on the liner layer, and a conductive material substantially filling the feature. The liner layer includes molybdenum (Mo) or W, and the interruption layer includes Mo.

公开(公告)号：US20240087955A1

公开(公告)日：2024-03-14

申请号：US18241343

申请日：2023-09-01

Applicant: Applied Materials, Inc.

Inventor： Yi XU ,  Xianyuan ZHAO ,  Zhimin QI ,  Aixi ZHANG ,  Geraldine VASQUEZ ,  Dien-Yeh WU ,  Wei LEI ,  Xingyao GAO ,  Shirish PETHE ,  Wenting HOU ,  Chao DU ,  Tsung-Han YANG ,  Kyoung-Ho BU ,  Chen-Han LIN ,  Jallepally RAVI ,  Yu LEI ,  Rongjun WANG ,  Xianmin TANG

IPC: H01L21/768

CPC classification number: H01L21/76879 ,  H01L21/76843 ,  H01L21/76856 ,  H01L21/76876

Abstract: A method and apparatus for forming tungsten features in semiconductor devices is provided. The method includes exposing a top opening of a feature formed in a substrate to a physical vapor deposition (PVD) process to deposit a tungsten liner layer within the feature. The PVD process is performed in a first processing region of a first processing chamber and the tungsten liner layer forms an overhang portion, which partially obstructs the top opening of the feature. The substrate is transferred from the first processing region of the first processing chamber to a second processing region of a second processing chamber without breaking vacuum. The overhang portion is exposed to nitrogen-containing radicals in the second processing region to inhibit subsequent growth of tungsten along the overhang portion. The feature is exposed to a tungsten-containing precursor gas to form a tungsten fill layer over the tungsten liner layer within the feature.

公开(公告)号：US20240047267A1

公开(公告)日：2024-02-08

申请号：US18228300

申请日：2023-07-31

Applicant: Applied Materials, Inc.

Inventor： Tsung-Han YANG ,  Shiyu YUE ,  Rongjun WANG

IPC: H01L21/768 ,  H01J37/32 ,  C23C14/56 ,  C23C14/58 ,  C23C16/06 ,  C23C14/06 ,  C23C16/455 ,  C23C14/18

CPC classification number: H01L21/76826 ,  H01L21/76843 ,  H01L21/76877 ,  H01J37/32091 ,  H01J37/32899 ,  C23C14/568 ,  C23C14/5846 ,  C23C16/06 ,  C23C14/0641 ,  C23C16/45525 ,  C23C14/18 ,  H01J2237/332

Abstract: Embodiments of methods and associated apparatus for filling features in a silicon-containing dielectric layer of a substrate are provided herein. In some embodiments, a method of filling features in a silicon-containing dielectric layer of a substrate includes: depositing a discontinuous liner layer in the feature via a physical vapor deposition (PVD) process in a first process chamber; performing a hydrogen plasma process in a second process chamber to form silicon-hydrogen bonds on surfaces of the feature not covered by the discontinuous liner layer; and depositing a bulk tungsten layer on the discontinuous liner layer and over the silicon-hydrogen bonds to fill the feature with tungsten in a third process chamber.

公开(公告)号：US20220310363A1

公开(公告)日：2022-09-29

申请号：US17838855

申请日：2022-06-13

Applicant: APPLIED MATERIALS, INC.

Inventor： Halbert CHONG ,  Rong TAO ,  Jianxin LEI ,  Rongjun WANG ,  Keith A. Miller ,  Irena H. Wysok ,  Tza-Jing Gung ,  Xing Chen

IPC: H01J37/32 ,  H01J37/34 ,  B08B5/00 ,  C23C14/50 ,  C23C14/34

Abstract: Methods and apparatus for cleaning a process kit configured for processing a substrate are provided. For example, a process chamber for processing a substrate can include a chamber wall; a sputtering target disposed in an upper section of the inner volume; a pedestal including a substrate support having a support surface to support a substrate below the sputtering target; a power source configured to energize sputtering gas for forming a plasma in the inner volume; a process kit surrounding the sputtering target and the substrate support; and an ACT connected to the pedestal and a controller configured to tune the pedestal using the ACT to maintain a predetermined potential difference between the plasma in the inner volume and the process kit, wherein the predetermined potential difference is based on a percentage of total capacitance of the ACT and a stray capacitance associated with a grounding path of the process chamber.

公开(公告)号：US20220013716A1

公开(公告)日：2022-01-13

申请号：US17486649

申请日：2021-09-27

Applicant: Applied Materials, Inc.

Inventor： Lin XUE ,  Jaesoo AHN ,  Mahendra PAKALA ,  Chi Hong CHING ,  Rongjun WANG

IPC: H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  H01F10/14 ,  H01F10/32

Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate in for spin-transfer-torque magnetoresistive random access memory (STT-MRAM) applications. In one example, a film stack utilized to form a magnetic tunnel junction structure on a substrate includes a pinned layer disposed on a substrate, wherein the pinned layer comprises multiple layers including at least one or more of a Co containing layer, Pt containing layer, Ta containing layer, an Ru containing layer, an optional structure decoupling layer disposed on the pinned magnetic layer, a magnetic reference layer disposed on the optional structure decoupling layer, a tunneling barrier layer disposed on the magnetic reference layer, a magnetic storage layer disposed on the tunneling barrier layer, and a capping layer disposed on the magnetic storage layer.

公开(公告)号：US20210320247A1

公开(公告)日：2021-10-14

申请号：US17307783

申请日：2021-05-04

Applicant: Applied Materials, Inc.

Inventor： Lin XUE ,  Chi Hong CHING ,  Xiaodong WANG ,  Mahendra PAKALA ,  Rongjun WANG

IPC: H01L43/12 ,  G11C11/16 ,  H01L27/22 ,  H01L27/12

Abstract: Embodiments of the disclosure provide methods for forming MTJ structures from a film stack disposed on a substrate for MRAM applications and associated MTJ devices. The methods described herein include forming the film properties of material layers from the film stack to create a film stack with a sufficiently high perpendicular magnetic anisotropy (PMA). An iron containing oxide capping layer is utilized to generate the desirable PMA. By utilizing an iron containing oxide capping layer, thickness of the capping layer can be more finely controlled and reliance on boron at the interface of the magnetic storage layer and the capping layer is reduced.

公开(公告)号：US20210319989A1

公开(公告)日：2021-10-14

申请号：US16846502

申请日：2020-04-13

Applicant: APPLIED MATERIALS, INC.

Inventor： Halbert CHONG ,  Rong TAO ,  Jianxin LEI ,  Rongjun WANG ,  Keith A. Miller ,  Irena H. Wysok ,  Tza-Jing Gung ,  Xing Chen

IPC: H01J37/32 ,  H01J37/34 ,  B08B5/00 ,  C23C14/50 ,  C23C14/34

Abstract: Methods and apparatus for cleaning a process kit configured for processing a substrate are provided. For example, a process chamber for processing a substrate can include a chamber wall; a sputtering target disposed in an upper section of the inner volume; a pedestal including a substrate support having a support surface to support a substrate below the sputtering target; a power source configured to energize sputtering gas for forming a plasma in the inner volume; a process kit surrounding the sputtering target and the substrate support; and an ACT connected to the pedestal and a controller configured to tune the pedestal using the ACT to maintain a predetermined potential difference between the plasma in the inner volume and the process kit, wherein the predetermined potential difference is based on a percentage of total capacitance of the ACT and a stray capacitance associated with a grounding path of the process chamber.

公开(公告)号：US20190172485A1

公开(公告)日：2019-06-06

申请号：US16272183

申请日：2019-02-11

Applicant: Applied Materials, Inc.

Inventor： Lin XUE ,  Chi Hong CHING ,  Jaesoo AHN ,  Mahendra PAKALA ,  Rongjun WANG

IPC: G11B5/39 ,  H01L21/768 ,  G11B5/31 ,  G11C11/15

Abstract: Embodiments herein provide methods of forming a magnetic tunnel junction structure. The method includes forming a film stack that includes: a buffer layer; a seed layer disposed over the buffer layer; a first pinning layer disposed over the seed layer; a synthetic ferrimagnet (SyF) coupling layer disposed over the first pinning layer; a second pinning layer disposed over the SyF coupling layer; a structure blocking layer disposed over the second pinning layer; a magnetic reference layer disposed over the structure blocking layer; a tunnel barrier layer disposed over the magnetic reference layer; a magnetic storage layer disposed over the tunnel barrier layer; a capping layer disposed over the magnetic storage layer; and a hard mask disposed over the capping layer, wherein at least one of the capping layer, the buffer layer, and the SyF coupling layer is not fabricated from Ru; and forming a magnetic tunnel junction structure.