公开(公告)号：US12002861B2

公开(公告)日：2024-06-04

申请号：US17626961

申请日：2020-07-07

Applicant: PARAGRAF LIMITED

Inventor： Hugh Glass ,  Ivor Guiney ,  Martin Tyler ,  Simon Thomas

IPC: H01L29/40 ,  H01L21/04 ,  H01L31/0216 ,  H01L31/0224 ,  H01L33/40 ,  H01L33/44 ,  H01L29/16 ,  H01L29/45

CPC classification number: H01L29/401 ,  H01L21/043 ,  H01L31/0216 ,  H01L31/0224 ,  H01L33/40 ,  H01L33/44 ,  H01L29/1606 ,  H01L29/45 ,  H01L2933/0016 ,  H01L2933/0025

Abstract: The present invention pro ides a method of providing an electrical contact on a graphene surface, the method comprising: (i) providing a graphene layer structure comprising one or more graphene layers and having a polymer coating on a surface thereof; (ii) contacting one or more portions of the polymer coating with a conductive metal-containing composition comprising a solvent, wherein the polymer coating is soluble in the solvent: and (iii) volatilising the solvent to deposit the conductive metal on the surface of the graphene layer structure.

公开(公告)号：US20240162040A1

公开(公告)日：2024-05-16

申请号：US18509043

申请日：2023-11-14

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Edoardo ZANETTI ,  Simone RASCUNA' ,  Mario Giuseppe SAGGIO ,  Alfio GUARNERA ,  Leonardo FRAGAPANE ,  Cristina TRINGALI

IPC: H01L21/04 ,  H01L21/285 ,  H01L29/06 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/872

CPC classification number: H01L21/046 ,  H01L21/0495 ,  H01L21/28537 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/66143 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/872 ,  H01L29/8725

Abstract: A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.

公开(公告)号：US11984499B2

公开(公告)日：2024-05-14

申请号：US17145969

申请日：2021-01-11

Applicant: Shanghai Hestia Power Inc.

Inventor： Chien-Chung Hung ,  Kuo-Ting Chu ,  Lurng-Shehng Lee ,  Chwan-Yin Li

IPC: H01L29/78 ,  H01L21/04 ,  H01L21/765 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L21/046 ,  H01L21/765 ,  H01L29/063 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/407 ,  H01L29/66068

Abstract: A trench silicon carbide metal-oxide semiconductor field effect transistor includes a silicon carbide semiconductor substrate and a trench metal-oxide semiconductor field effect transistor, the field effect transistor includes a trench vertically arranged and penetrating along a first horizontal direction, a gate insulating layer formed on an inner wall of the trench, a first poly gate formed on the gate insulating layer, a shield region formed outsides and below the trench, and a field plate arranged between a bottom wall of the trench and the shield region, and the field plate has semiconductor doping and is laterally in contact to a current spreading layer to deplete electrons of the current spreading layer when a reverse bias voltage is applied.

公开(公告)号：US20240145537A1

公开(公告)日：2024-05-02

申请号：US17977003

申请日：2022-10-31

Applicant: Wolfspeed, Inc.

Inventor： Rahul R. Potera ,  Matthew McCain ,  Madankumar Sampath ,  Steven Rogers

IPC: H01L29/06 ,  H01L21/04 ,  H01L29/16 ,  H01L29/34 ,  H01L29/66 ,  H01L29/772

CPC classification number: H01L29/0661 ,  H01L21/045 ,  H01L21/046 ,  H01L21/0475 ,  H01L29/1608 ,  H01L29/34 ,  H01L29/66068 ,  H01L29/7722

Abstract: A method of forming a semiconductor device includes etching a semiconductor layer to form a plurality of mesa stripes in the semiconductor layer. The plurality of mesa stripes extend in a first direction and include mesa sidewalls that extend in the first direction and mesa surfaces at opposite ends of the mesa stripes. An additional mesa region is formed at an end of at least one of the mesa stripes. The additional mesa region is electrically insulated from the at least one of the mesa stripes. A semiconductor device structure includes a plurality of mesa stripes that extend in a first direction and include mesa sidewalls that extend in the first direction and mesa end surfaces at opposite ends of the mesa stripes. An additional mesa region that is electrically insulated from the at least one of the mesa stripes is at an end of at least one of the mesa stripes.

公开(公告)号：US20240128323A1

公开(公告)日：2024-04-18

申请号：US18546853

申请日：2022-02-18

Applicant: THE RESEARCH FOUNDATION FOR THE STATE UNIVERSTIY OF NEW YORK

Inventor： Woongje SUNG ,  Dongyoung KIM ,  Adam MORGAN

IPC: H01L29/10 ,  H01L21/04 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1095 ,  H01L21/047 ,  H01L29/0607 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7832

Abstract: Metal oxide semiconductor field effect transistors (MOSFET) including deep P-wells are disclosed. MOSFETs may include a drift layer disposed over a substrate, and a P-well disposed within the drift layer. The P-well may include a first portion disposed directly over the drift layer, where the first portion includes a first doping concentration. The P-well may also include a second portion separated from the drift layer by the first portion. The second portion may include a second doping concentration distinct from the first doping concentration of the first portion. Additionally, the MOSFET may include an N-source disposed at least partially over the second portion of the P-well, an oxide layer disposed over the N-source and the drift layer, and a gate layer disposed over the oxide layer.

公开(公告)号：US11929229B2

公开(公告)日：2024-03-12

申请号：US18196548

申请日：2023-05-12

Applicant: mi2-factory GmbH

Inventor： Florian Krippendorf ,  Constantin Csato

IPC: H01J37/317 ,  C23C14/18 ,  C23C14/48 ,  H01J37/05 ,  H01J37/147 ,  H01J37/20 ,  H01L21/04 ,  H01L29/32

CPC classification number: H01J37/05 ,  C23C14/18 ,  C23C14/48 ,  H01J37/1477 ,  H01J37/20 ,  H01J37/317 ,  H01J37/3171 ,  H01L21/046 ,  H01L29/32 ,  H01J2237/024 ,  H01J2237/057 ,  H01J2237/1518 ,  H01J2237/20214

Abstract: A semiconductor wafer includes a first surface and an implantation area adjacent to the first surface and a certain distance away from the first surface, the implantation area including implanted particles and defects. A defect concentration in the implantation area deviates by less than 5% from a maximum defect concentration in the implantation area.

公开(公告)号：US20240072125A1

公开(公告)日：2024-02-29

申请号：US17893277

申请日：2022-08-23

Applicant: Wolfspeed, Inc.

Inventor： Kyle Bothe ,  Evan Jones ,  Chris Hardiman

IPC: H01L29/40 ,  H01L21/02 ,  H01L21/04 ,  H01L21/285 ,  H01L29/16 ,  H01L29/20 ,  H01L29/45

CPC classification number: H01L29/401 ,  H01L21/0217 ,  H01L21/0485 ,  H01L21/28575 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/45 ,  H01L29/452

Abstract: A method of forming ohmic contacts on a semiconductor layer includes forming silicon ohmic contact precursors on the semiconductor layer, depositing a layer of metal on the semiconductor layer including the silicon ohmic contact precursors, reacting the layer of metal with the silicon ohmic contact precursors to form metal silicide ohmic contacts on the semiconductor layer, and selectively removing the layer of metal from the semiconductor layer without removing the metal silicide contacts from the semiconductor layer.

公开(公告)号：US20240072108A1

公开(公告)日：2024-02-29

申请号：US18270483

申请日：2021-11-18

Applicant: ROHM CO., LTD.

Inventor： Yuki NAKANO ,  Hiroaki SHIRAGA ,  Kenji YAMAMOTO

IPC: H01L29/06 ,  H01L21/04 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/872

CPC classification number: H01L29/0623 ,  H01L21/047 ,  H01L29/0634 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/872

Abstract: An SiC semiconductor device includes an SiC semiconductor chip that has a main surface, an n-type drift region that is formed in a surface layer portion of the main surface and has an impurity concentration adjusted by at least two types of pentavalent elements, and a p-type impurity region that is formed inside the drift region such as to form a pn-junction portion with the drift region.

公开(公告)号：US11901618B2

公开(公告)日：2024-02-13

申请号：US17929907

申请日：2022-09-06

Applicant: InnoLux Corporation

Inventor： Chia-Ping Tseng ,  Ker-Yih Kao ,  Chia-Chi Ho ,  Ming-Yen Weng ,  Hung-I Tseng ,  Shu-Ling Wu ,  Huei-Ying Chen

IPC: H01Q1/38 ,  H01Q3/44 ,  H01Q9/04 ,  H01L27/12 ,  H01L21/04 ,  H01Q3/34 ,  G02F1/1343 ,  G02F1/1333

CPC classification number: H01Q1/38 ,  G02F1/13439 ,  H01L21/045 ,  H01L27/1237 ,  H01Q3/34 ,  H01Q3/44 ,  H01Q9/0407 ,  G02F1/133345 ,  G02F2201/07

Abstract: An electronic device is provided. The electronic device includes a first substrate, a multilayer structure, and a passivation layer. The multilayer structure is disposed on the first substrate. The multilayer structure includes a first conductive layer and a second conductive layer disposed on the first conductive layer. The passivation layer is disposed on the second conductive layer. In addition, a thermal expansion coefficient of the second conductive layer is between a thermal expansion coefficient of the first conductive layer and a thermal expansion coefficient of the passivation layer.

公开(公告)号：US11901444B2

公开(公告)日：2024-02-13

申请号：US17661843

申请日：2022-05-03

Applicant: Mitsubishi Electric Corporation

Inventor： Ryu Kamibaba ,  Tetsuo Takahashi ,  Akihiko Furukawa

IPC: H01L29/739 ,  H01L29/78 ,  H01L29/08 ,  H01L27/06 ,  H01L21/04

CPC classification number: H01L29/7397 ,  H01L21/0465 ,  H01L27/0629 ,  H01L29/083 ,  H01L29/7813

Abstract: Examples of a semiconductor device includes a transistor region formed in a semiconductor substrate having a first conductivity type drift layer, and a diode region formed to be adjacent to the transistor region in the semiconductor substrate, wherein the diode region has a second conductivity type anode layer formed on the drift layer and a first conductivity type cathode layer formed on the lower side of the drift layer, and the cathode layer has an adjacent region contacting the transistor region, the adjacent region having a depth, from a lower surface of the semiconductor substrate, which becomes shallower toward the transistor region and having first conductivity type impurity concentration which decreases toward the transistor region.