公开(公告)号：US10050042B2

公开(公告)日：2018-08-14

申请号：US15170562

申请日：2016-06-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Fang Chen ,  Kuo-Chiang Ting ,  Jhon Jhy Liaw ,  Min-Chang Liang

IPC: H01L27/11 ,  H01L23/522 ,  H01L27/088 ,  H01L23/528 ,  H01L21/8238 ,  H01L27/11582 ,  H01L49/02

Abstract: An embodiment is an integrated circuit structure including a static random access memory (SRAM) cell having a first number of semiconductor fins, the SRAM cell having a first boundary and a second boundary parallel to each other, and a third boundary and a fourth boundary parallel to each other, the SRAM cell having a first cell height as measured from the third boundary to the fourth boundary, and a logic cell having the first number of semiconductor fins and the first cell height.

公开(公告)号：US09805984B2

公开(公告)日：2017-10-31

申请号：US15380376

申请日：2016-12-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Joanna Chaw Yane Yin ,  Chi-Hsi Wu ,  Kuo-Chiang Ting ,  Chen Kuang-Hsin

IPC: H01L21/8234 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092

CPC classification number: H01L21/823481 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/6681

Abstract: The present disclosure provides many different embodiments of a FinFET device that provide one or more improvements over the prior art. In one embodiment, a FinFET includes a semiconductor substrate and a plurality of fins having a first height and a plurality of fin having a second height on the semiconductor substrate. The second height may be less than the first height.

公开(公告)号：US20170221905A1

公开(公告)日：2017-08-03

申请号：US15170562

申请日：2016-06-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Fang Chen ,  Kuo-Chiang Ting ,  Jhon Jhy Liaw ,  Min-Chang Liang

IPC: H01L27/11 ,  H01L23/522 ,  H01L21/8238 ,  H01L27/088 ,  H01L23/528

CPC classification number: H01L27/1104 ,  H01L21/823821 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0886 ,  H01L27/1116 ,  H01L27/11582 ,  H01L28/00

Abstract: An embodiment is an integrated circuit structure including a static random access memory (SRAM) cell having a first number of semiconductor fins, the SRAM cell having a first boundary and a second boundary parallel to each other, and a third boundary and a fourth boundary parallel to each other, the SRAM cell having a first cell height as measured from the third boundary to the fourth boundary, and a logic cell having the first number of semiconductor fins and the first cell height.

公开(公告)号：US09659810B2

公开(公告)日：2017-05-23

申请号：US14248403

申请日：2014-04-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Joanna Chaw Yane Yin ,  Chi-Hsi Wu ,  Kuo-Chiang Ting ,  Chen Kuang-Hsin

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/8238 ,  H01L21/84

CPC classification number: H01L21/823481 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/6681

Abstract: The present disclosure provides many different embodiments of fabricating a FinFET device that provide one or more improvements over the prior art. In one embodiment, a method of fabricating a FinFET includes providing a semiconductor substrate and a plurality of dummy fins and active fins on the semiconductor substrate. A predetermined group of dummy fins is removed.

公开(公告)号：US20160293762A1

公开(公告)日：2016-10-06

申请号：US15181139

申请日：2016-06-13

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hou-Ju Li ,  Kao-Ting Lai ,  Kuo-Chiang Ting ,  Chi-Hsi Wu

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L29/167 ,  H01L29/08 ,  H01L29/161

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: An integrated circuit device includes a fin having a gate area beneath a gate electrode structure, a source/drain region disposed beyond ends of the fin, and a first conformal layer formed around an embedded portion of the source/drain region. A vertical sidewall of the first conformal layer is oriented parallel to the gate area.

Abstract translation: 集成电路器件包括鳍状物，栅极电极结构下方具有栅极区域，设置在鳍状物的末端以外的源极/漏极区域以及围绕源极/漏极区域的嵌入部分形成的第一共形层。 第一共形层的垂直侧壁平行于栅极区域定向。

公开(公告)号：US20160155739A1

公开(公告)日：2016-06-02

申请号：US14557261

申请日：2014-12-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Kuo-Chiang Ting ,  Jyh-Huei Chen ,  Wen-Huei Guo ,  Cheng-Han Wu ,  Yu-Wei Lee

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/6681

Abstract: An embodiment is a method including forming a first fin on a substrate, the first fin having a first longitudinal axis, forming a first trench having a first width in the first fin, the first trench dividing the first fin into at least two fin portions, forming a first gate structure and first source/drain regions over one of the at least two fin portions of the first fin, and forming a second gate structure and second source/drain regions over another of the at least two fin portions of the first fin.

Abstract translation: 一个实施例是一种方法，包括在衬底上形成第一鳍片，第一鳍片具有第一纵向轴线，在第一鳍片中形成具有第一宽度的第一沟槽，第一沟槽将第一鳍片分成至少两个翅片部分， 在第一鳍片的至少两个翅片部分中的一个上形成第一栅极结构和第一源极/漏极区域，并且在第一鳍片的至少两个翅片部分中的另一个上形成第二栅极结构和第二源极/漏极区域 。

公开(公告)号：US11462418B2

公开(公告)日：2022-10-04

申请号：US16745610

申请日：2020-01-17

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih Ting Lin ,  Szu-Wei Lu ,  Weiming Chris Chen ,  Kuo-Chiang Ting ,  Shang-Yun Hou ,  Chi-Hsi Wu

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L23/14 ,  H01L25/065 ,  H01L21/768 ,  H01L23/538 ,  H01L23/31

Abstract: A method includes attaching semiconductor devices to an interposer structure, attaching the interposer structure to a first carrier substrate, attaching integrated passive devices to the first carrier substrate, forming an encapsulant over the semiconductor devices and the integrated passive devices, debonding the first carrier substrate, attaching the encapsulant and the semiconductor devices to a second carrier substrate, forming a first redistribution structure on the encapsulant, the interposer structure, and the integrated passive devices, wherein the first redistribution structure contacts the interposer structure and the integrated passive devices, and forming external connectors on the first redistribution structure.

公开(公告)号：US10546786B2

公开(公告)日：2020-01-28

申请号：US16111408

申请日：2018-08-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Joanna Chaw Yane Yin ,  Chi-Hsi Wu ,  Kuo-Chiang Ting ,  Kuang-Hsin Chen

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/092 ,  H01L27/088 ,  H01L21/84 ,  H01L21/762 ,  H01L21/8238

Abstract: In an embodiment, a method for fabricating a FinFET device includes providing a semiconductor substrate, etching the semiconductor substrate to form dummy fins and active fins. The group of dummy fins is etched through a patterned mask layer. An isolation feature is formed on the semiconductor substrate after etching the first group of dummy fins.

公开(公告)号：US20200003950A1

公开(公告)日：2020-01-02

申请号：US16450725

申请日：2019-06-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chen-Hua Yu ,  Hsing-Kuo Hsia ,  Kuo-Chiang Ting ,  Pin-Tso Lin ,  Sung-Hui Huang ,  Shang-Yun Hou ,  Chi-Hsi Wu

IPC: G02B6/12 ,  G02B6/124 ,  G02B6/136 ,  G02B6/122

Abstract: A method includes forming silicon waveguide sections in a first oxide layer over a substrate, the first oxide layer disposed on the substrate, forming a routing structure over the first oxide layer, the routing structure including one or more insulating layers and one or more conductive features in the one or more insulating layers, recessing regions of the routing structure, forming nitride waveguide sections in the recessed regions of the routing structure, wherein the nitride waveguide sections extend over the silicon waveguide sections, forming a second oxide layer over the nitride waveguide sections, and attaching semiconductor dies to the routing structure, the dies electrically connected to the conductive features.

公开(公告)号：US10515888B2

公开(公告)日：2019-12-24

申请号：US15707301

申请日：2017-09-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Kuo-Chiang Ting ,  Chi-Hsi Wu ,  Shang-Yun Hou ,  Tu-Hao Yu ,  Chia-Hao Hsu ,  Pin-Tso Lin ,  Chia-Hsin Chen

IPC: H01L23/498 ,  H01L21/683 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00

Abstract: A semiconductor device includes a dielectric interposer, a first interconnection layer, an electronic component, a plurality of electrical conductors and a plurality of conductive structures. The dielectric interposer has a first surface and a second surface opposite to the first surface. The first interconnection layer is over the first surface of the dielectric interposer. The electronic component is over and electrically connected to the first interconnection layer. The electrical conductors are over the second surface of the dielectric interposer. The conductive structures are through the dielectric interposer, wherein the conductive structures are electrically connected to the first interconnection layer and the electrical conductors.