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公开(公告)号：US09577009B1
公开(公告)日：2017-02-21
申请号：US14940421
申请日：2015-11-13
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Sheng-Hung Shih , Kuo-Chi Tu , Chih-Yang Chang , Hsia-Wei Chen , Chin-Chieh Yang , Jen-Sheng Yang , Wen-Ting Chu , Yu-Wen Liao
CPC classification number: H01L45/1273 , G11C13/003 , G11C13/0038 , G11C13/0069 , G11C13/0097 , G11C2013/0071 , G11C2013/0083 , G11C2213/79 , H01L27/2427 , H01L27/2436 , H01L27/2481 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/1266 , H01L45/146 , H01L45/16 , H01L45/1675
Abstract: The present disclosure relates to an integrated chip comprising an RRAM cell that is driven by a PMOS transistor, and an associated method of formation. In some embodiments, the integrated chip has a PMOS transistor arranged within a semiconductor substrate. A resistive RRAM cell is arranged within an inter-level dielectric (ILD) layer overlying the semiconductor substrate. The RRAM cell has a first conductive electrode separated from a second conductive electrode by a dielectric data storage layer having a variable resistance. The first conductive electrode is connected to a drain terminal of the PMOS transistor by one or more metal interconnect layers. The use of a PMOS transistor to drive the RRAM cell allows for impact of the body effect to be reduced and therefore allows for a reset operation to be performed at a low power and in a short amount of time.
Abstract translation: 本公开涉及包括由PMOS晶体管驱动的RRAM单元的集成芯片以及相关联的形成方法。 在一些实施例中，集成芯片具有布置在半导体衬底内的PMOS晶体管。 电阻RRAM单元布置在覆盖半导体衬底的层间电介质（ILD）层内。 RRAM单元具有通过具有可变电阻的介电数据存储层与第二导电电极分离的第一导电电极。 第一导电电极通过一个或多个金属互连层连接到PMOS晶体管的漏极端子。 使用PMOS晶体管来驱动RRAM单元允许减小体效应的影响，因此允许以低功率和短时间执行复位操作。
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公开(公告)号：US09553265B1
公开(公告)日：2017-01-24
申请号：US14995294
申请日：2016-01-14
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Jen-Sheng Yang , Chih-Yang Chang , Chin-Chieh Yang , Kuo-Chi Tu , Sheng-Hung Shih , Wen-Ting Chu , Yu-Wen Liao , Manish Kumar Singh
CPC classification number: H01L45/1253 , H01L27/2436 , H01L45/08 , H01L45/122 , H01L45/146 , H01L45/1666 , H01L45/1691
Abstract: The present disclosure relates to an integrated circuit, which includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a lower metal layer, an intermediate metal layer disposed over the lower metal layer, and an upper metal layer disposed over the intermediate metal layer. An upper surface of the lower metal layer and a lower surface of the intermediate metal layer are spaced vertically apart by a first distance. A resistive random access memory (RRAM) cell is arranged between the lower metal layer and the upper metal layer. The RRAM cell includes a bottom electrode and a top electrode which are separated by a data storage layer having a variable resistance. The data storage layer vertically spans a second distance that is greater than the first distance.
Abstract translation: 本公开涉及集成电路，其包括设置在半导体衬底上的半导体衬底和互连结构。 互连结构包括下金属层，设置在下金属层上的中间金属层和设置在中间金属层上的上金属层。 下金属层的上表面和中间金属层的下表面间隔开第一距离。 电阻随机存取存储器（RRAM）单元布置在下金属层和上金属层之间。 RRAM单元包括由具有可变电阻的数据存储层分离的底部电极和顶部电极。 数据存储层垂直地跨越大于第一距离的第二距离。
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公开(公告)号：US09425392B2
公开(公告)日：2016-08-23
申请号：US14803377
申请日：2015-07-20
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chih-Yang Chang , Wen-Ting Chu , Kuo-Chi Tu , Yu-Wen Liao , Hsia-Wei Chen , Chin-Chieh Yang , Sheng-Hung Shih , Wen-Chun You
CPC classification number: H01L45/124 , H01L27/2436 , H01L45/04 , H01L45/06 , H01L45/065 , H01L45/08 , H01L45/085 , H01L45/10 , H01L45/12 , H01L45/1206 , H01L45/1213 , H01L45/122 , H01L45/1226 , H01L45/1233 , H01L45/1246 , H01L45/1253 , H01L45/126 , H01L45/1266 , H01L45/1273 , H01L45/1286 , H01L45/1293 , H01L45/14 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/149 , H01L45/16 , H01L45/1608 , H01L45/1616 , H01L45/1625 , H01L45/1633 , H01L45/1641 , H01L45/165 , H01L45/1658 , H01L45/1666 , H01L45/1675 , H01L45/1683 , H01L45/1691
Abstract: The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell. The method forms a bottom electrode over a bottom electrode via. The method further forms a variable resistive dielectric layer over the bottom electrode, and a top electrode over the variable resistive dielectric layer. The method forms a top electrode via vertically extending outward from an upper surface of the top electrode at a position centered along a first axis that is laterally offset from a second axis centered upon the bottom electrode via. The top electrode via has a smaller width than the top electrode. Laterally offsetting the top electrode via from the bottom electrode via provides the top electrode via with good contact resistance.
Abstract translation: 本公开涉及一种形成电阻随机存取存储器（RRAM）单元的方法。 该方法在底部电极通孔上形成底部电极。 该方法进一步在底部电极上形成可变电阻介质层，以及在可变电阻介质层上形成顶部电极。 该方法通过从顶部电极的上表面向外垂直延伸的形式形成顶部电极，所述顶部电极沿着第一轴线位于以与底部电极通孔为中心的第二轴线侧向偏移的位置。 顶部电极通孔具有比顶部电极更小的宽度。 顶部电极通孔从底部电极通过提供顶部电极通孔具有良好的接触电阻。
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公开(公告)号：US09112148B2
公开(公告)日：2015-08-18
申请号：US14041514
申请日：2013-09-30
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chih-Yang Chang , Wen-Ting Chu , Kuo-Chi Tu , Yu-Wen Liao , Hsia-Wei Chen , Chin-Chieh Yang , Sheng-Hung Shih , Wen-Chun You
IPC: H01L45/00
CPC classification number: H01L45/124 , H01L27/2436 , H01L45/04 , H01L45/06 , H01L45/065 , H01L45/08 , H01L45/085 , H01L45/10 , H01L45/12 , H01L45/1206 , H01L45/1213 , H01L45/122 , H01L45/1226 , H01L45/1233 , H01L45/1246 , H01L45/1253 , H01L45/126 , H01L45/1266 , H01L45/1273 , H01L45/1286 , H01L45/1293 , H01L45/14 , H01L45/141 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/149 , H01L45/16 , H01L45/1608 , H01L45/1616 , H01L45/1625 , H01L45/1633 , H01L45/1641 , H01L45/165 , H01L45/1658 , H01L45/1666 , H01L45/1675 , H01L45/1683 , H01L45/1691
Abstract: The present disclosure relates to a resistive random access memory (RRAM) cell architecture, with off-axis or laterally offset top electrode via (TEVA) and bottom electrode via (BEVA). Traditional RRAM cells having a TEVA and BEVA that are on-axis can cause high contact resistance variations. The off-axis TEVA and BEVA in the current disclosure pushes the TEVA away from the insulating layer over the RRAM cell, which can improve the contact resistance variations. The present disclosure also relates to a memory device having a rectangular shaped RRAM cell having a larger area that can lower the forming voltage and improve data retention.
Abstract translation: 本发明涉及一种电阻随机存取存储器（RRAM）单元体系结构，具有通过（TEVA）的离轴或横向偏移的顶部电极和通过（BEVA）的底部电极。 具有在轴上的TEVA和BEVA的传统RRAM电池可能导致高接触电阻变化。 本公开中的离轴TEVA和BEVA通过RRAM单元推动TEVA远离绝缘层，这可以改善接触电阻的变化。 本公开还涉及一种具有矩形形状的RRAM单元的存储器件，其具有可以降低形成电压并改善数据保持的较大面积。
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公开(公告)号：US20150144859A1
公开(公告)日：2015-05-28
申请号：US14087082
申请日：2013-11-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Hsia-Wei Chen , Wen-Ting Chu , Kuo-Chi Tu , Chih-Yang Chang , Chin-Chieh Yang , Yu-Wen Liao , Wen-Chun You , Sheng-Hung Shih
CPC classification number: H01L45/1233 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/12 , H01L45/122 , H01L45/124 , H01L45/1253 , H01L45/146 , H01L45/147 , H01L45/16 , H01L45/1666 , H01L45/1683
Abstract: An integrated circuit device including a resistive random access memory (RRAM) cell formed over a substrate. The RRAM cell includes a top electrode having an upper surface. A blocking layer covers a portion of the upper surface. A via extends above the top electrode within a matrix of dielectric. The upper surface of the top electrode includes an area that interfaces with the blocking layer and an area that interfaces with the via. The area of the upper surface that interfaces with the via surrounds the area of the upper surface that interfaces with the blocking layer. The blocking layer is functional during processing to protect the RRAM cell from etch damage while being structured in such a way as to not interfere with contact between the overlying via and the top electrode.
Abstract translation: 一种包括在衬底上形成的电阻随机存取存储器（RRAM）单元的集成电路器件。 RRAM单元包括具有上表面的顶电极。 阻挡层覆盖上表面的一部分。 通孔在电介质矩阵内在顶部电极上方延伸。 顶部电极的上表面包括与阻挡层接触的区域和与通孔相接合的区域。 与通孔相接的上表面的区域围绕与阻挡层相接的上表面区域。 阻挡层在处理期间是功能性的，以保护RRAM单元免受蚀刻损伤，同时以不妨碍上覆通孔和顶部电极之间的接触的方式构造。
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Patent Agency Ranking
公开(公告)号：US11849588B2
公开(公告)日：2023-12-19
申请号：US17712543
申请日：2022-04-04
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Fu-Chen Chang , Kuo-Chi Tu , Tzu-Yu Chen , Sheng-Hung Shih
CPC classification number: H10B51/30 , G11C11/223 , H01L28/57 , H01L28/60 , H10B51/10 , H10B53/00 , H10B53/30
Abstract: A method of forming a semiconductor device includes forming an inter-metal dielectric layer over a substrate; forming a first conductive line embedded in the inter-metal dielectric layer; forming a dielectric structure over the inter-metal dielectric layer and the first conductive line; etching the dielectric structure until the first conductive line is exposed; forming a bottom electrode layer on the exposed first conductive line such that the bottom electrode layer has an U-shaped when viewed in a cross section; forming a ferroelectric layer over the bottom electrode layer; forming a top electrode layer over the ferroelectric layer.
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公开(公告)号：US11723213B2
公开(公告)日：2023-08-08
申请号：US17376531
申请日：2021-07-15
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tzu-Yu Chen , Kuo-Chi Tu , Sheng-Hung Shih , Fu-Chen Chang
Abstract: Some embodiments relate to a ferroelectric random access memory (FeRAM) device. The FeRAM device includes a bottom electrode structure and a top electrode overlying the ferroelectric structure. The top electrode has a first width as measured between outermost sidewalls of the top electrode. A ferroelectric structure separates the bottom electrode structure from the top electrode. The ferroelectric structure has a second width as measured between outermost sidewalls of the ferroelectric structure. The second width is greater than the first width such that the ferroelectric structure includes a ledge that reflects a difference between the first width and the second width. A dielectric sidewall spacer structure is disposed on the ledge and covers the outermost sidewalls of the top electrode.
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公开(公告)号：US11296116B2
公开(公告)日：2022-04-05
申请号：US16727673
申请日：2019-12-26
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Fu-Chen Chang , Kuo-Chi Tu , Tzu-Yu Chen , Sheng-Hung Shih
IPC: H01L27/11 , H01L27/1159 , H01L27/11587 , G11C11/22 , H01L49/02 , H01L27/11507 , H01L27/11502
Abstract: A semiconductor device includes an inter-metal dielectric layer, a first conductive line, and a first ferroelectric random access memory (FRAM) structure. The first conductive line is embedded in the inter-metal dielectric layer and extends along a first direction. The first FRAM structure is over inter-metal dielectric layer and includes a bottom electrode layer, a ferroelectric layer, and a top electrode layer. The bottom electrode layer is over the first conductive line and has an U-shaped when viewed in a cross section taken along a second direction substantially perpendicular to the first direction. The ferroelectric layer is conformally formed on the bottom electrode. The top electrode layer is over the ferroelectric layer.
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公开(公告)号：US11227872B2
公开(公告)日：2022-01-18
申请号：US16394207
申请日：2019-04-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chih-Hsiang Chang , Kuo-Chi Tu , Sheng-Hung Shih , Wen-Ting Chu , Tzu-Yu Chen , Fu-Chen Chang
Abstract: In some embodiments, the present disclosure relates to an integrated chip including one or more lower interconnect layers arranged within one or more stacked inter-layer dielectric layers over a substrate. A bottom electrode is disposed over the one or more interconnect layers, and a top electrode is disposed over the bottom electrode. A ferroelectric layer is disposed between and contacts a first surface of the bottom electrode and a second surface of the top electrode. The ferroelectric layer includes a protrusion that extends past outer surfaces of the top electrode and the bottom electrode along a first direction that is perpendicular to a second direction that is normal to the first surface. The protrusion is confined between lines that extend along the first and second surface.
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公开(公告)号：US11195840B2
公开(公告)日：2021-12-07
申请号：US16452965
申请日：2019-06-26
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tzu-Yu Chen , Kuo-Chi Tu , Sheng-Hung Shih , Wen-Ting Chu , Yong-Shiuan Tsair
IPC: H01L27/11507 , H01L49/02
Abstract: Some embodiments relate to a ferroelectric random access memory (FeRAM) device. The FeRAM device includes a bottom electrode structure and a top electrode overlying the ferroelectric structure. The top electrode has a first width as measured between outermost sidewalls of the top electrode. A ferroelectric structure separates the bottom electrode structure from the top electrode. The ferroelectric structure has a second width as measured between outermost sidewalls of the ferroelectric structure. The second width is greater than the first width such that the ferroelectric structure includes a ledge that reflects a difference between the first width and the second width. A dielectric sidewall spacer structure is disposed on the ledge and covers the outermost sidewalls of the top electrode.
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