公开(公告)号：US20250022773A1

公开(公告)日：2025-01-16

申请号：US18492142

申请日：2023-10-23

Applicant: Samsung Electronics Co., Ltd

Inventor： JINTAE KIM ,  Seungchan Yun ,  Kang-ill Seo

IPC: H01L23/48 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Integrated circuit devices and methods of forming the same are provided. The integrated circuit devices may include an upper transistor including an upper channel region on a substrate, a lower transistor between the substrate and the upper transistor, the lower transistor including a lower channel region, and a power line extending longitudinally in a first horizontal direction. At least one of the upper channel region or the lower channel region may extend longitudinally in a second horizontal direction that traverses the first horizontal direction, and the at least one of the upper channel region or the lower channel region may overlap the power line in a thickness direction.

公开(公告)号：US12094869B2

公开(公告)日：2024-09-17

申请号：US18366010

申请日：2023-08-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghak Hong ,  Seungchan Yun ,  Kang-ill Seo

IPC: H01L27/02 ,  H01L21/8238 ,  H01L27/07 ,  H01L29/739 ,  H01L29/861

CPC classification number: H01L27/0255 ,  H01L21/823807 ,  H01L21/823885 ,  H01L27/0727 ,  H01L29/7391 ,  H01L29/861

Abstract: Diode structures of stacked devices and methods of forming the same are provided. Diode structures may include a substrate, an upper semiconductor layer that is spaced apart from the substrate in a vertical direction, an upper thin semiconductor layer protruding from a side surface of the upper semiconductor layer in a first horizontal direction, a lower semiconductor layer that is between the substrate and the upper semiconductor layer and has a first conductivity type, a lower thin semiconductor layer protruding from a side surface of the lower semiconductor layer in the first horizontal direction, a first diode contact that is electrically connected to the lower semiconductor layer, and a second diode contact that is electrically connected to one of the upper semiconductor layer and a portion of the substrate. The one of the upper semiconductor layer and the portion of the substrate may have a second conductivity type.

公开(公告)号：US20240282855A1

公开(公告)日：2024-08-22

申请号：US18228231

申请日：2023-07-31

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Myunghoon JUNG ,  Panjae Park ,  Jaejik Baek ,  Seungchan Yun ,  Myung Yang ,  Kang-ill Seo

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L29/0847 ,  H01L29/41741 ,  H01L29/66666

Abstract: Provided is a semiconductor device including a 3DSFET device which includes: a 1st source/drain region; a 2nd source/drain region, above the 1st source/drain region, having a smaller width than the 1st source/drain region, the 2nd source/drain region being isolated from the 1st source/drain region by a 1st isolation structure; a 1st contact plug on the 1st source/drain region; a 2nd contact plug on the 2nd source/drain region; and a 2nd isolation structure, between the 1st contact plug and the 2nd contact plug, isolating the 2nd contact plug from the 1st contact plug, wherein the 2nd isolation structure is different and separate from the 1st isolation structure.

公开(公告)号：US20240096889A1

公开(公告)日：2024-03-21

申请号：US18173847

申请日：2023-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Min Song ,  Seungchan Yun ,  Kang-ill Seo

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L27/0922 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: Integrated circuit devices may include a first upper channel region on a substrate, a first lower channel region between the substrate and the first upper channel region, a first intergate insulator that is between the first lower channel region and the first upper channel region and includes a lower portion and an upper portion, an upper gate electrode, and a lower gate electrode between the substrate and the upper gate electrode. The first upper channel region and the upper portion of the first intergate insulator may be in the upper gate electrode. The first lower channel region and the lower portion of the first intergate insulator are in the lower gate electrode.

公开(公告)号：US20240072048A1

公开(公告)日：2024-02-29

申请号：US18184901

申请日：2023-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungchan Yun ,  Seungmin Song ,  Myunghoon Jung ,  Keumseok Park ,  Kang-ill Seo

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L27/088 ,  H01L21/823412 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/78696

Abstract: An integrated circuit device may comprise an upper transistor that is on a substrate. The upper transistor may comprise an upper channel region. The integrated circuit device may further comprise a lower transistor that is between the substrate and the upper transistor. The lower transistor may comprise a lower channel region. The integrated circuit device may further include an integrated insulator that is between the lower channel region and the upper channel region. The integrated insulator may comprise an outer layer and an inner layer in the outer layer, wherein the inner layer and the outer layer comprise different materials.

公开(公告)号：US20230335556A1

公开(公告)日：2023-10-19

申请号：US17841510

申请日：2022-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghak Hong ,  Seungchan Yun ,  Kang-ill Seo

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/324 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/0922 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/775 ,  H01L21/02603 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/3247 ,  H01L21/8221 ,  H01L21/823807 ,  H01L29/66439 ,  H01L29/66742

Abstract: A CMOS device including a substrate comprising a shallow trench isolation region, an nFET on the substrate above the shallow trench isolation region, and a pFET. The nFET includes a source region, a drain region, a channel region including a series of nanowires extending from the source region to the drain region, and a gate region around the series of nanowires of the channel region. The nanowires include a first series of nanowires in a first column and a second series of nanowires in a second column adjacent to the first column. The pFET includes a source region, a drain region, a channel region extending from the source region to the drain region, and a gate region on the channel region.

公开(公告)号：US11769830B2

公开(公告)日：2023-09-26

申请号：US17038020

申请日：2020-09-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungchan Yun ,  Donghwan Han

IPC: H01L29/78 ,  H01L27/06 ,  H01L27/088 ,  H01L21/822 ,  H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L27/12 ,  H01L21/8234

CPC classification number: H01L29/7827 ,  H01L21/8221 ,  H01L21/823412 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/124 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/78642 ,  H01L29/78696

Abstract: A semiconductor device includes a plurality of channel layers disposed on an active region of a substrate and spaced apart from each other in a first direction, a first gate structure surrounding the plurality of channel layers, first source/drain regions disposed on the active region on both lateral sides of the first gate structure and contacting the plurality of channel layers and spaced apart from each other in a second direction, an element isolation layer disposed on an upper portion of the first gate structure, a semiconductor layer disposed on the element isolation layer and having a vertical region extending in the first direction and including second source/drain regions spaced apart from each other in the first direction, and a second gate structure disposed to surround a portion of the vertical region. The semiconductor device further includes first to fourth contact plugs.

公开(公告)号：US20230275021A1

公开(公告)日：2023-08-31

申请号：US17738393

申请日：2022-05-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： BYOUNGHAK HONG ,  Jeonghyuk Yim ,  Inchan Hwang ,  Gilhwan Son ,  Seungyoung Lee ,  Saehan Park ,  Janggeun Lee ,  Myunghoon Jung ,  Seungchan Yun ,  Buhyun Ham ,  Kang-ILL Seo

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/302 ,  H01L21/8234

CPC classification number: H01L23/5286 ,  H01L23/5283 ,  H01L23/5226 ,  H01L21/302 ,  H01L21/823475

Abstract: Integrated circuit devices may include a transistor, a passive device, a substrate extending between the transistor and the passive device and a power rail. The passive device may be spaced apart from the substrate. Each of the passive device and the power rail may have a first surface facing the substrate, and the first surface of the passive device is closer than the first surface of the power rail to the substrate.

公开(公告)号：US20230135219A1

公开(公告)日：2023-05-04

申请号：US17570920

申请日：2022-01-07

Applicant: Samsung Electronics Co., Ltd

Inventor： Byounghak Hong ,  Seungchan Yun ,  Inchan Hwang ,  Hyoeun Park ,  Kang-ill Seo

IPC: H01L27/07 ,  H01L27/08 ,  H01L27/06 ,  H01L49/02 ,  H01L25/07

Abstract: Resistor structures of stacked devices and methods of forming the same are provided. The, resistor structures may include a substrate, an upper semiconductor layer that may be spaced apart from the substrate in a vertical direction, a lower semiconductor layer that may be between the substrate and the upper semiconductor layer, and first and second resistor contacts that may be spaced apart from each other in a horizontal direction. At least one of the upper semiconductor layer, the lower semiconductor layer, and a portion of the substrate may contact the first and second resistor contacts.

公开(公告)号：US20230095421A1

公开(公告)日：2023-03-30

申请号：US17547700

申请日：2021-12-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghak Hong ,  Hoonseok Seo ,  Seungchan Yun ,  Inchan Hwang ,  Kang-ill Seo

IPC: H01L27/06 ,  H01L23/528 ,  H01L23/48 ,  H01L21/8234 ,  H01L49/02

Abstract: Integrated circuit devices including a metal resistor and methods of forming the same are provided. The integrated circuit devices may include a substrate including a first surface and a second surface that is opposite the first surface and is parallel to the first surface, a transistor including a gate electrode, first and second resistor contacts that are spaced apart from each other in a horizontal direction that is parallel to the second surface of the substrate, and a metal resistor. The first surface of the substrate may face the gate electrode. The metal resistor may include a third surface and a fourth surface that is parallel to the third surface and the second surface of the substrate, and the fourth surface of the metal resistor may be closer to the second surface than the first surface and contacts the first and second resistor contacts.