公开(公告)号：US11139382B2

公开(公告)日：2021-10-05

申请号：US16732520

申请日：2020-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Gil Yang ,  Seung Min Song ,  Soo Jin Jeong ,  Dong Il Bae ,  Bong Seok Suh

IPC: H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  H01L27/12

Abstract: A semiconductor device having a gate-all-around structure includes a first fin pattern and a second fin pattern separated by a first trench and extending in a first direction, a first nanosheet on the first fin pattern, a second nanosheet on the second fin pattern, a first fin liner extending along at least a portion of a sidewall and a bottom surface of the first trench, a first field insulation layer disposed on the first fin liner and filling a portion of the first trench, and a first gate structure overlapping an end portion of the first fin pattern and including a first gate spacer. A height from the bottom surface of the first trench to a lower surface of the first gate spacer is greater than a height from the bottom surface of the first trench to an upper surface of the first field insulation layer.

公开(公告)号：US10243040B1

公开(公告)日：2019-03-26

申请号：US15964170

申请日：2018-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo Seok Park ,  Seung Min Song ,  Jung Gil Yang ,  Geum Jong Bae ,  Dong Il Bae

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/417

Abstract: A semiconductor device including a transistor disposed on a first region of a substrate, the transistor including source/drain regions, a plurality of channel layers spaced apart from each other in a direction perpendicular to an upper surface of the substrate while connecting the source/drain regions, respectively, a gate electrode surrounding each of the plurality of channel layers, and a gate insulator between the gate electrode and the plurality of channel layers; and a non-active component disposed on a second region of the substrate, the non-active component including a fin structure including an a plurality of first semiconductor patterns alternately stacked with a plurality of second semiconductor patterns, an epitaxial region adjacent to the fin structure, a non-active electrode intersecting the fin structure, and a blocking insulation film between the non-active electrode and the fin structure.

公开(公告)号：US10014393B2

公开(公告)日：2018-07-03

申请号：US15361110

申请日：2016-11-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Min Song ,  Dong Chan Suh ,  Jung Gil Yang ,  Geum Jong Bae ,  Woo Bin Song

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L29/66795 ,  H01L29/0676 ,  H01L29/4236 ,  H01L29/42392 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/78696

Abstract: A method of manufacturing semiconductor device includes forming a plurality of sacrificial layers and a plurality of semiconductor layers repeatedly and alternately stacked on a substrate, partially removing the sacrificial layers, forming spacers in removed regions of the sacrificial layers, and replacing remaining portions of the sacrificial layers with a gate electrode. Each of the sacrificial layers includes first portions disposed adjacent to the plurality of semiconductor layers and a second portions disposed between the first portions. The second portion having a different composition from the first portions.

公开(公告)号：US11710770B2

公开(公告)日：2023-07-25

申请号：US17575918

申请日：2022-01-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo Cheol Shin ,  Sun Wook Kim ,  Seung Min Song ,  Nam Hyun Lee

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/423 ,  H01L27/092

CPC classification number: H01L29/0673 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42392

Abstract: A semiconductor device includes a substrate having a first region and a second region, first and second nanowires disposed sequentially on the substrate in the first region, and extending respectively in a first direction, third and fourth nanowires disposed sequentially on the substrate in the second region, and extending respectively in the first direction, a first inner spacer between the first nanowire and the second nanowire, and including hydrogen of a first hydrogen mole fraction, and a second inner spacer between the third nanowire and the fourth nanowire, and including hydrogen of a second hydrogen mole fraction that is greater than the first hydrogen mole fraction.

公开(公告)号：US11699728B2

公开(公告)日：2023-07-11

申请号：US17127230

申请日：2020-12-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang Woo Noh ,  Seung Min Song ,  Geum Jong Bae ,  Dong Il Bae

IPC: H01L29/66 ,  H01L29/417 ,  H01L21/768 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/76897 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7853 ,  H01L2029/7858

Abstract: A semiconductor device including a fin field effect transistor (fin-FET) includes active fins disposed on a substrate, isolation layers on both sides of the active fins, a gate structure formed to cross the active fins and the isolation layers, source/drain regions on the active fins on sidewalls of the gate structure, a first interlayer insulating layer on the isolation layers in contact with portions of the sidewalls of the gate structure and portions of surfaces of the source/drain regions, an etch stop layer configured to overlap the first interlayer insulating layer, the sidewalls of the gate structure, and the source/drain regions, and contact plugs formed to pass through the etch stop layer to contact the source/drain regions. The source/drain regions have main growth portions in contact with upper surfaces of the active fins.

公开(公告)号：US10181510B2

公开(公告)日：2019-01-15

申请号：US15726535

申请日：2017-10-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung Gil Yang ,  Seung Min Song ,  Sung Min Kim ,  Woo Seok Park ,  Geum Jong Bae ,  Dong Il Bae

IPC: H01L29/76 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

Abstract: A method of manufacturing a semiconductor device is provided. A stacked structure including one or more sacrificial layers and one or more semiconductor layers are stacked on a substrate is formed. A dummy gate structure including a dummy gate and a dummy spacer on the stacked structure is formed. The stacked structure is etched using the dummy gate structure to form a first recess. The one or more sacrificial layers are etched. The dummy spacer is removed. A spacer film is formed on the dummy gate, the one or more semiconductor layer and the one or more sacrificial layers. The semiconductor layer and spacer film are etched to form a second recess using the dummy gate and spacer film. An external spacer formed on the dummy gate and an internal spacer formed on the one or more sacrificial layers are formed. A source/drain region is formed in the second recess.

公开(公告)号：US09929235B1

公开(公告)日：2018-03-27

申请号：US15463551

申请日：2017-03-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Gil Yang ,  Dong Il Bae ,  Chang Woo Sohn ,  Seung Min Song ,  Dong Hun Lee

IPC: H01L29/76 ,  H01L29/06 ,  H01L29/423 ,  H01L27/088 ,  H01L27/02 ,  H01L27/092 ,  H01L29/10 ,  H01L29/165 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/82385 ,  H01L27/0207 ,  H01L27/0883 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0669 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/785

Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, a first nanowire spaced apart from a first region of the substrate, a first gate electrode surrounding a periphery of the first nanowire, a second nanowire spaced apart from a second region of the substrate and extending in a first direction and having a first width in a second direction intersecting the first direction, a supporting pattern contacting the second nanowire and positioned under the second nanowire, and a second gate electrode extending in the second direction and surrounding the second nanowire and the supporting pattern.

公开(公告)号：US12107135B2

公开(公告)日：2024-10-01

申请号：US17467660

申请日：2021-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Gil Yang ,  Seung Min Song ,  Soo Jin Jeong ,  Dong Il Bae ,  Bong Seok Suh

IPC: H01L29/423 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0642 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78696

Abstract: A semiconductor device having a gate-all-around structure includes a first fin pattern and a second fin pattern separated by a first trench and extending in a first direction, a first nanosheet on the first fin pattern, a second nanosheet on the second fin pattern, a first fin liner extending along at least a portion of a sidewall and a bottom surface of the first trench, a first field insulation layer disposed on the first fin liner and filling a portion of the first trench, and a first gate structure overlapping an end portion of the first fin pattern and including a first gate spacer. A height from the bottom surface of the first trench to a lower surface of the first gate spacer is greater than a height from the bottom surface of the first trench to an upper surface of the first field insulation layer.

公开(公告)号：US11640973B2

公开(公告)日：2023-05-02

申请号：US17508197

申请日：2021-10-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Gil Yang ,  Dong Il Bae ,  Chang Woo Sohn ,  Seung Min Song ,  Dong Hun Lee

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/165 ,  H01L29/10 ,  H01L27/092 ,  H01L27/02 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, a first nanowire spaced apart from a first region of the substrate, a first gate electrode surrounding a periphery of the first nanowire, a second nanowire spaced apart from a second region of the substrate and extending in a first direction and having a first width in a second direction intersecting the first direction, a supporting pattern contacting the second nanowire and positioned under the second nanowire, and a second gate electrode extending in the second direction and surrounding the second nanowire and the supporting pattern.

公开(公告)号：US11164943B2

公开(公告)日：2021-11-02

申请号：US16928439

申请日：2020-07-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Gil Yang ,  Dong Il Bae ,  Chang Woo Sohn ,  Seung Min Song ,  Dong Hun Lee

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/165 ,  H01L29/10 ,  H01L27/092 ,  H01L27/02 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, a first nanowire spaced apart from a first region of the substrate, a first gate electrode surrounding a periphery of the first nanowire, a second nanowire spaced apart from a second region of the substrate and extending in a first direction and having a first width in a second direction intersecting the first direction, a supporting pattern contacting the second nanowire and positioned under the second nanowire, and a second gate electrode extending in the second direction and surrounding the second nanowire and the supporting pattern.