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公开(公告)号:US11967614B2
公开(公告)日:2024-04-23
申请号:US17715273
申请日:2022-04-07
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jung Gil Yang , Seung Min Song , Soo Jin Jeong , Dong Il Bae , Bong Seok Suh
IPC: H01L29/08 , H01L29/04 , H01L29/786
CPC classification number: H01L29/0847 , H01L29/045 , H01L29/78696
Abstract: Provided is a semiconductor device comprising an active region on a substrate and including first and second sidewalls extending in a first direction and an epitaxial pattern on the active region, wherein the epitaxial pattern includes first and second epitaxial sidewalls extending from the first and second sidewalls, respectively, the first epitaxial sidewall includes a first epitaxial lower sidewall, a first epitaxial upper sidewall, and a first epitaxial connecting sidewall connecting the first epitaxial lower sidewall and the first epitaxial upper sidewall, the second epitaxial sidewall includes a second epitaxial lower sidewall, a second epitaxial upper sidewall, and a second epitaxial connecting sidewall connecting the second epitaxial lower sidewall and the second epitaxial upper sidewall, a distance between the first and second epitaxial upper sidewalls decreases away from the active region, and the first and second epitaxial lower sidewalls extend in parallel to a top surface of the substrate.
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公开(公告)号:US11322589B2
公开(公告)日:2022-05-03
申请号:US16752418
申请日:2020-01-24
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jung Gil Yang , Seung Min Song , Soo Jin Jeong , Dong Il Bae , Bong Seok Suh
IPC: H01L29/78 , H01L29/66 , H01L21/308 , H01L21/02 , H01L21/3065 , H01L29/08 , H01L29/04 , H01L29/786
Abstract: Provided is a semiconductor device comprising an active region on a substrate and including first and second sidewalls extending in a first direction and an epitaxial pattern on the active region, wherein the epitaxial pattern includes first and second epitaxial sidewalls extending from the first and second sidewalls, respectively, the first epitaxial sidewall includes a first epitaxial lower sidewall, a first epitaxial upper sidewall, and a first epitaxial connecting sidewall connecting the first epitaxial lower sidewall and the first epitaxial upper sidewall, the second epitaxial sidewall includes a second epitaxial lower sidewall, a second epitaxial upper sidewall, and a second epitaxial connecting sidewall connecting the second epitaxial lower sidewall and the second epitaxial upper sidewall, a distance between the first and second epitaxial upper sidewalls decreases away from the active region, and the first and second epitaxial lower sidewalls extend in parallel to a top surface of the substrate.
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公开(公告)号:US20190067490A1
公开(公告)日:2019-02-28
申请号:US15900175
申请日:2018-02-20
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jung Gil Yang , Woo Seok PARK , Dong Chan SUH , Seung Min SONG , Geum Jong BAE , Dong II BAE
IPC: H01L29/786 , H01L29/423 , H01L29/08 , H01L29/161 , H01L29/10
Abstract: A semiconductor device includes a substrate, a plurality of channel layers stacked on the substrate, a gate electrode surrounding the plurality of channel layers, and embedded source/drain layers on opposing sides of the gate electrode. The embedded source/drain layers each have a first region and a second region on the first region. The second region has a plurality of layers having different compositions.
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公开(公告)号:US20220310852A1
公开(公告)日:2022-09-29
申请号:US17840737
申请日:2022-06-15
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jung Gil Yang , Woo Seok PARK , Dong Chan SUH , Seung Min SONG , Geum Jong BAE , Dong Il BAE
IPC: H01L29/786 , H01L29/423 , H01L29/10 , H01L29/161 , H01L29/08 , H01L29/66 , H01L29/775 , B82Y10/00 , H01L29/06
Abstract: A semiconductor device includes a substrate, a plurality of channel layers stacked on the substrate, a gate electrode surrounding the plurality of channel layers, and embedded source/drain layers on opposing sides of the gate electrode. The embedded source/drain layers each have a first region and a second region on the first region. The second region has a plurality of layers having different compositions.
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公开(公告)号:US11139382B2
公开(公告)日:2021-10-05
申请号:US16732520
申请日:2020-01-02
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jung Gil Yang , Seung Min Song , Soo Jin Jeong , Dong Il Bae , Bong Seok Suh
IPC: H01L27/088 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/49 , H01L29/51 , H01L29/775 , H01L29/78 , H01L29/786 , H01L27/12
Abstract: A semiconductor device having a gate-all-around structure includes a first fin pattern and a second fin pattern separated by a first trench and extending in a first direction, a first nanosheet on the first fin pattern, a second nanosheet on the second fin pattern, a first fin liner extending along at least a portion of a sidewall and a bottom surface of the first trench, a first field insulation layer disposed on the first fin liner and filling a portion of the first trench, and a first gate structure overlapping an end portion of the first fin pattern and including a first gate spacer. A height from the bottom surface of the first trench to a lower surface of the first gate spacer is greater than a height from the bottom surface of the first trench to an upper surface of the first field insulation layer.
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公开(公告)号:US10243040B1
公开(公告)日:2019-03-26
申请号:US15964170
申请日:2018-04-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Woo Seok Park , Seung Min Song , Jung Gil Yang , Geum Jong Bae , Dong Il Bae
IPC: H01L29/66 , H01L29/06 , H01L29/78 , H01L29/417
Abstract: A semiconductor device including a transistor disposed on a first region of a substrate, the transistor including source/drain regions, a plurality of channel layers spaced apart from each other in a direction perpendicular to an upper surface of the substrate while connecting the source/drain regions, respectively, a gate electrode surrounding each of the plurality of channel layers, and a gate insulator between the gate electrode and the plurality of channel layers; and a non-active component disposed on a second region of the substrate, the non-active component including a fin structure including an a plurality of first semiconductor patterns alternately stacked with a plurality of second semiconductor patterns, an epitaxial region adjacent to the fin structure, a non-active electrode intersecting the fin structure, and a blocking insulation film between the non-active electrode and the fin structure.
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公开(公告)号:US10014393B2
公开(公告)日:2018-07-03
申请号:US15361110
申请日:2016-11-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Seung Min Song , Dong Chan Suh , Jung Gil Yang , Geum Jong Bae , Woo Bin Song
IPC: H01L21/336 , H01L29/66 , H01L29/06 , H01L29/423 , H01L29/49
CPC classification number: H01L29/66795 , H01L29/0676 , H01L29/4236 , H01L29/42392 , H01L29/495 , H01L29/66545 , H01L29/6656 , H01L29/66666 , H01L29/78696
Abstract: A method of manufacturing semiconductor device includes forming a plurality of sacrificial layers and a plurality of semiconductor layers repeatedly and alternately stacked on a substrate, partially removing the sacrificial layers, forming spacers in removed regions of the sacrificial layers, and replacing remaining portions of the sacrificial layers with a gate electrode. Each of the sacrificial layers includes first portions disposed adjacent to the plurality of semiconductor layers and a second portions disposed between the first portions. The second portion having a different composition from the first portions.
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公开(公告)号:US11683925B2
公开(公告)日:2023-06-20
申请号:US17387192
申请日:2021-07-28
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jung Gil Yang , Sun Wook Kim , Jun Beom Park , Tae Young Kim , Geum Jong Bae
IPC: H01L23/528 , H01L29/06 , H01L29/786 , H01L29/775 , B82Y10/00 , H01L27/02 , H01L29/423 , H10B10/00
CPC classification number: H10B10/125 , H01L23/528
Abstract: A semiconductor device includes first and second fin type patterns, first and second gate patterns intersecting the first and second fin type patterns, third and fourth gate patterns intersecting the first fin type pattern between the first and the second gate patterns, a fifth gate pattern intersecting the second fin type pattern, a sixth gate pattern intersecting the second fin type pattern, first to third semiconductor patterns disposed among the first, the third, the fourth and the second gate patterns, and fourth to sixth semiconductor patterns disposed among the first, the fifth, the sixth and the second gate patterns. The first semiconductor pattern to the fourth semiconductor pattern and the sixth semiconductor pattern are electrically connected to a wiring structure, and the fifth semiconductor pattern is not connected to the wiring structure.
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公开(公告)号:US11024628B2
公开(公告)日:2021-06-01
申请号:US16405174
申请日:2019-05-07
Applicant: Samsung Electronics Co., Ltd.
Inventor: Chang Woo Noh , Myung Gil Kang , Geum Jong Bae , Dong Il Bae , Jung Gil Yang , Sang Hoon Lee
IPC: H01L27/092 , H01L29/78 , H01L29/66 , H01L21/033 , H01L21/8238 , H01L29/10 , H01L29/08
Abstract: Semiconductor devices are provided. The semiconductor devices may include a first wire pattern extending in a first direction on a substrate and a second wire pattern on the first wire pattern. The second wire pattern may be spaced apart from the first wire pattern and extends in the first direction. The semiconductor devices may also include a first gate structure at least partially surrounding the first wire pattern and the second wire pattern, a second gate structure spaced apart from the first gate structure in the first direction, a first source/drain region between the first gate structure and the second gate structure, a first spacer between a bottom surface of the first source/drain region and the substrate, a first source/drain contact on the first source/drain region, and a second spacer between the first source/drain contact and the first gate structure.
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公开(公告)号:US10181510B2
公开(公告)日:2019-01-15
申请号:US15726535
申请日:2017-10-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Jung Gil Yang , Seung Min Song , Sung Min Kim , Woo Seok Park , Geum Jong Bae , Dong Il Bae
IPC: H01L29/76 , H01L29/06 , H01L29/49 , H01L29/66 , H01L29/786
Abstract: A method of manufacturing a semiconductor device is provided. A stacked structure including one or more sacrificial layers and one or more semiconductor layers are stacked on a substrate is formed. A dummy gate structure including a dummy gate and a dummy spacer on the stacked structure is formed. The stacked structure is etched using the dummy gate structure to form a first recess. The one or more sacrificial layers are etched. The dummy spacer is removed. A spacer film is formed on the dummy gate, the one or more semiconductor layer and the one or more sacrificial layers. The semiconductor layer and spacer film are etched to form a second recess using the dummy gate and spacer film. An external spacer formed on the dummy gate and an internal spacer formed on the one or more sacrificial layers are formed. A source/drain region is formed in the second recess.
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