公开(公告)号：US11935924B2

公开(公告)日：2024-03-19

申请号：US17371582

申请日：2021-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Noh Yeong Park ,  Dong Il Bae ,  Beomjin Park

IPC: H01L29/10 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/1033 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/41775 ,  H01L29/42364 ,  H01L29/42372

Abstract: Disclosed are semiconductor devices and/or method of fabricating the same. The semiconductor device comprises a substrate including first and second regions, a first active pattern on the first region and including a pair of first source/drain patterns and a first channel pattern including first semiconductor patterns, a second active pattern on the second region and including a pair of second source/drain patterns and a second channel pattern including second semiconductor patterns, a support pattern between two vertically adjacent first semiconductor patterns, and a first gate electrode and a second gate electrode on the first channel pattern and the second channel pattern. A channel length of the first channel pattern is greater than that of the second channel pattern. A ratio of a width of the support pattern to the channel length of the first channel pattern is in a range of 0.05 to 0.2.

公开(公告)号：US11637205B2

公开(公告)日：2023-04-25

申请号：US17140786

申请日：2021-01-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junggil Yang ,  Seungmin Song ,  Geumjong Bae ,  Dong Il Bae

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/417 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device includes a channel pattern including a first semiconductor pattern and a second semiconductor pattern, which are sequentially stacked on a substrate, and a gate electrode that extends in a first direction and crosses the channel pattern. The gate electrode includes a first portion interposed between the substrate and the first semiconductor pattern and a second portion interposed between the first and second semiconductor patterns. A maximum width in a second direction of the first portion is greater than a maximum width in the second direction of the second portion, and a maximum length in the second direction of the second semiconductor pattern is less than a maximum length in the second direction of the first semiconductor pattern.

公开(公告)号：US11139382B2

公开(公告)日：2021-10-05

申请号：US16732520

申请日：2020-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung Gil Yang ,  Seung Min Song ,  Soo Jin Jeong ,  Dong Il Bae ,  Bong Seok Suh

IPC: H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  H01L27/12

Abstract: A semiconductor device having a gate-all-around structure includes a first fin pattern and a second fin pattern separated by a first trench and extending in a first direction, a first nanosheet on the first fin pattern, a second nanosheet on the second fin pattern, a first fin liner extending along at least a portion of a sidewall and a bottom surface of the first trench, a first field insulation layer disposed on the first fin liner and filling a portion of the first trench, and a first gate structure overlapping an end portion of the first fin pattern and including a first gate spacer. A height from the bottom surface of the first trench to a lower surface of the first gate spacer is greater than a height from the bottom surface of the first trench to an upper surface of the first field insulation layer.

公开(公告)号：US10243040B1

公开(公告)日：2019-03-26

申请号：US15964170

申请日：2018-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Woo Seok Park ,  Seung Min Song ,  Jung Gil Yang ,  Geum Jong Bae ,  Dong Il Bae

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/417

Abstract: A semiconductor device including a transistor disposed on a first region of a substrate, the transistor including source/drain regions, a plurality of channel layers spaced apart from each other in a direction perpendicular to an upper surface of the substrate while connecting the source/drain regions, respectively, a gate electrode surrounding each of the plurality of channel layers, and a gate insulator between the gate electrode and the plurality of channel layers; and a non-active component disposed on a second region of the substrate, the non-active component including a fin structure including an a plurality of first semiconductor patterns alternately stacked with a plurality of second semiconductor patterns, an epitaxial region adjacent to the fin structure, a non-active electrode intersecting the fin structure, and a blocking insulation film between the non-active electrode and the fin structure.

公开(公告)号：US09972720B2

公开(公告)日：2018-05-15

申请号：US15252040

申请日：2016-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong Il Bae

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L29/78609 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78603 ,  H01L29/78654 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate. A planar insulating layer is disposed on an upper surface of the substrate. A channel region is disposed above the planar insulating layer. A gate electrode is disposed on the channel region. The semiconductor device includes a source region and a drain region. Each of the source region and the drain region is disposed on the substrate and is connected to the channel region. The planar insulating layer has a length equal to or greater than a length of the channel region, and the planar insulating layer includes first and second insulating layers having different permittivities.

公开(公告)号：US11699728B2

公开(公告)日：2023-07-11

申请号：US17127230

申请日：2020-12-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang Woo Noh ,  Seung Min Song ,  Geum Jong Bae ,  Dong Il Bae

IPC: H01L29/66 ,  H01L29/417 ,  H01L21/768 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/41791 ,  H01L21/76897 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7853 ,  H01L2029/7858

Abstract: A semiconductor device including a fin field effect transistor (fin-FET) includes active fins disposed on a substrate, isolation layers on both sides of the active fins, a gate structure formed to cross the active fins and the isolation layers, source/drain regions on the active fins on sidewalls of the gate structure, a first interlayer insulating layer on the isolation layers in contact with portions of the sidewalls of the gate structure and portions of surfaces of the source/drain regions, an etch stop layer configured to overlap the first interlayer insulating layer, the sidewalls of the gate structure, and the source/drain regions, and contact plugs formed to pass through the etch stop layer to contact the source/drain regions. The source/drain regions have main growth portions in contact with upper surfaces of the active fins.

公开(公告)号：US11133383B2

公开(公告)日：2021-09-28

申请号：US16741868

申请日：2020-01-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chang Woo Noh ,  Dong Il Bae ,  Geum Jong Bae

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/311 ,  H01L21/84 ,  H01L27/12 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device including a buried insulating layer on a substrate; a lower semiconductor layer on the buried insulating layer, the lower semiconductor layer including a first material; a channel pattern on the lower semiconductor layer, the channel pattern being spaced apart from the lower semiconductor layer and including a second material different from the first material; and a gate electrode surrounding at least a portion of the channel pattern.

公开(公告)号：US11024628B2

公开(公告)日：2021-06-01

申请号：US16405174

申请日：2019-05-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Woo Noh ,  Myung Gil Kang ,  Geum Jong Bae ,  Dong Il Bae ,  Jung Gil Yang ,  Sang Hoon Lee

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/033 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/08

Abstract: Semiconductor devices are provided. The semiconductor devices may include a first wire pattern extending in a first direction on a substrate and a second wire pattern on the first wire pattern. The second wire pattern may be spaced apart from the first wire pattern and extends in the first direction. The semiconductor devices may also include a first gate structure at least partially surrounding the first wire pattern and the second wire pattern, a second gate structure spaced apart from the first gate structure in the first direction, a first source/drain region between the first gate structure and the second gate structure, a first spacer between a bottom surface of the first source/drain region and the substrate, a first source/drain contact on the first source/drain region, and a second spacer between the first source/drain contact and the first gate structure.

公开(公告)号：US10453756B2

公开(公告)日：2019-10-22

申请号：US15937037

申请日：2018-03-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mirco Cantoro ,  Maria Toledano Luque ,  Yeoncheol Heo ,  Dong Il Bae

IPC: H01L21/308 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L27/11 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/161 ,  H01L29/417

Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor layer on a substrate, the semiconductor layer including a first semiconductor material and a second semiconductor material, patterning the semiconductor layer to form a preliminary active pattern, oxidizing at least two sidewalls of the preliminary active pattern to form an oxide layer on each of the at least two sidewalls of the preliminary active pattern, at least two upper patterns and a semiconductor pattern being formed in the preliminary active pattern when the oxide layers are formed, the semiconductor pattern being disposed between the at least two upper patterns, and removing the semiconductor pattern to form an active pattern, the active pattern including the at least two upper patterns. A concentration of the second semiconductor material in each of the at least two upper patterns is higher than a concentration of the second semiconductor material in the semiconductor pattern.

公开(公告)号：US10181510B2

公开(公告)日：2019-01-15

申请号：US15726535

申请日：2017-10-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung Gil Yang ,  Seung Min Song ,  Sung Min Kim ,  Woo Seok Park ,  Geum Jong Bae ,  Dong Il Bae

IPC: H01L29/76 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L29/786

Abstract: A method of manufacturing a semiconductor device is provided. A stacked structure including one or more sacrificial layers and one or more semiconductor layers are stacked on a substrate is formed. A dummy gate structure including a dummy gate and a dummy spacer on the stacked structure is formed. The stacked structure is etched using the dummy gate structure to form a first recess. The one or more sacrificial layers are etched. The dummy spacer is removed. A spacer film is formed on the dummy gate, the one or more semiconductor layer and the one or more sacrificial layers. The semiconductor layer and spacer film are etched to form a second recess using the dummy gate and spacer film. An external spacer formed on the dummy gate and an internal spacer formed on the one or more sacrificial layers are formed. A source/drain region is formed in the second recess.