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    DATA READING METHOD, AND CONTROL CIRCUIT, MEMORY MODULE AND MEMORY STORAGE APPARATUS AND MEMORY MODULE USING THE SAME
    32.
    发明申请
    DATA READING METHOD, AND CONTROL CIRCUIT, MEMORY MODULE AND MEMORY STORAGE APPARATUS AND MEMORY MODULE USING THE SAME 有权
    数据读取方法和控制电路，存储器模块和存储器存储器和使用其的存储器模块

    公开(公告)号：US20140293696A1

    公开(公告)日：2014-10-02

    申请号：US13901571

    申请日：2013-05-24

    Applicant: PHISON ELECTRONICS CORP.

    Inventor： Wei Lin ,  Tien-Ching Wang ,  Kuo-Hsin Lai ,  Yu-Cheng Hsu ,  Kuo-Yi Cheng

    IPC: G11C16/26

    CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/3436 ,  G11C16/349

    Abstract: A data reading method for a rewritable non-volatile memory module is provided. The method includes applying a test voltage to a word line of the rewritable non-volatile memory module to read a plurality of verification bit data. The method also includes calculating a variation of bit data identified as a first status among the verification bit data, obtaining a new read voltage value set based on the variation, and updating a threshold voltage set for the word line with the new read voltage value set. The method further includes using the updated threshold voltage set to read data from a physical page formed by memory cells connected to the word line. Accordingly, storage states of memory cells in the rewritable non-volatile memory module can be identified correctly, thereby preventing data stored in the memory cells from losing.

    Abstract translation: 提供了一种可重写非易失性存储器模块的数据读取方法。 该方法包括将测试电压施加到可重写非易失性存储器模块的字线以读取多个验证位数据。 该方法还包括计算在验证位数据中识别为第一状态的位数据的变化，获得基于该变化设置的新的读取电压值，并且用新的读取电压值集更新用于字线的阈值电压 。 该方法还包括使用更新的阈值电压来从连接到字线的存储器单元形成的物理页读取数据。 因此，可以正确地识别可重写非易失性存储器模块中的存储单元的存储状态，从而防止存储在存储单元中的数据丢失。

    Data reading method, and control circuit, memory module and memory storage apparatus using the same
    33.
    发明授权
    Data reading method, and control circuit, memory module and memory storage apparatus using the same 有权
    数据读取方法和控制电路，存储器模块和使用其的存储器存储装置

    公开(公告)号：US08830750B1

    公开(公告)日：2014-09-09

    申请号：US13928356

    申请日：2013-06-26

    Applicant: Phison Electronics Corp.

    Inventor： Kuo-Yi Cheng ,  Wei Lin ,  Yu-Hsiang Lin ,  Shao-Wei Yen ,  Kuo-Hsin Lai

    IPC: G11C16/06 ,  G11C16/08 ,  G11C16/26

    CPC classification number: G11C16/26 ,  G11C11/5642 ,  G11C16/0483 ,  G11C2211/5621

    Abstract: A data reading method for a rewritable non-volatile memory module is provided. The method includes determining a corresponding read voltage based on a critical voltage distribution of memory cells of a word line. The method further includes: if the critical voltage distribution of the memory cells is a right-offset distribution, applying a set of right adjustment read voltage to the word line to read a plurality of bit data as corresponding soft values; and decoding the corresponding soft values to obtain page data stored in the memory cells. Herein, the set of right adjustment read voltage includes a plurality of positive adjustment read voltages and a plurality of negative adjustment read voltages and the number of the positive adjustment read voltages is more than the number of the negative adjustment read voltages. Accordingly, storage states of the memory cells can be identified correctly.

    Abstract translation: 提供了一种可重写非易失性存储器模块的数据读取方法。 该方法包括基于字线的存储器单元的临界电压分布来确定相应的读取电压。 该方法还包括：如果存储器单元的临界电压分布是右偏移分布，则将一组正确的调整读取电压施加到字线以读取多个位数据作为相应的软值; 并解码对应的软值以获得存储在存储单元中的页面数据。 这里，正确调整读取电压的集合包括多个正调整读取电压和多个负调整读取电压，并且正调整读取电压的数量大于负调整读取电压的数量。 因此，可以正确地识别存储器单元的存储状态。

    Decoding method, memory storage device and memory control circuit unit
    34.
    发明授权
    Decoding method, memory storage device and memory control circuit unit 有权

    公开(公告)号：US10534665B2

    公开(公告)日：2020-01-14

    申请号：US15884407

    申请日：2018-01-31

    Applicant: PHISON ELECTRONICS CORP.

    Inventor： Yu-Hsiang Lin ,  Shao-Wei Yen ,  Cheng-Che Yang ,  Kuo-Hsin Lai

    IPC: G06F11/10 ,  H03M13/37 ,  H03M13/45 ,  G11C29/52

    Abstract: A decoding method for a memory storage device including a rewritable non-volatile memory module is provided according to an exemplary embodiment of the invention. The method includes: reading at least one memory cells by using at least one read voltage level to obtain a codeword; performing a parity check operation on the codeword by an error checking and correcting circuit to generate a syndrome sum corresponding to the codeword; and dynamically adjusting a first parameter used by the error checking and correcting circuit in a first decoding operation based on whether the syndrome sum is less than a first threshold value and performing the first decoding operation on the codeword by the error checking and correcting circuit by using the first parameter.

    Decoding method, memory control circuit unit and memory storage apparatus
    35.
    发明授权
    Decoding method, memory control circuit unit and memory storage apparatus 有权

    公开(公告)号：US10409674B2

    公开(公告)日：2019-09-10

    申请号：US15084454

    申请日：2016-03-29

    Applicant: PHISON ELECTRONICS CORP.

    Inventor： Wei Lin ,  Tien-Ching Wang ,  Kuo-Hsin Lai

    IPC: G11C29/00 ,  G06F11/10 ,  G06F3/06 ,  G11C29/52 ,  G11C11/56 ,  G11C29/04

    Abstract: A decoding method for a rewritable non-volatile memory module is provided. The method includes reading data from a plurality of memory cells of the rewritable non-volatile memory module according to a first voltage, wherein the data includes a user data string and an error checking and correcting code set. The method also includes decoding at least part of sub data units i the user data string according to a first decoding algorithm to obtain a plurality of decoded sub data units. The method further includes restoring a value of the corrected bit to an original bit value if a corrected bit in the decoded sub data units matches a reliability condition.

    Data processing method, memory storage device and memory control circuit unit
    36.
    发明授权
    Data processing method, memory storage device and memory control circuit unit 有权

    公开(公告)号：US10116335B2

    公开(公告)日：2018-10-30

    申请号：US15188995

    申请日：2016-06-22

    Applicant: PHISON ELECTRONICS CORP.

    Inventor： Yu-Hsiang Lin ,  Cheng-Che Yang ,  Shao-Wei Yen ,  Kuo-Hsin Lai

    IPC: H03M13/00 ,  H03M13/29 ,  G06F11/10 ,  H03M13/11 ,  G11C29/52 ,  G11C29/00

    Abstract: A data processing method, a memory storage device and a memory control circuit unit are provided. The method includes: receiving first write data; performing a first stage encoding operation of a low-density parity-check (LDPC) code on the first write data and generating first transition data; performing a second stage encoding operation of the LDPC code on the first transition data and generating a first error correcting code (ECC); receiving second write data; and performing the first stage encoding operation of the LDPC code on the second write data during a time period of performing the second stage encoding operation of the LDPC code on the first transition data. Accordingly, the data processing efficiency corresponding to the LDPC code can be improved.

    Decoding method, memory storage device and memory control circuit unit
    37.
    发明授权
    Decoding method, memory storage device and memory control circuit unit 有权

    公开(公告)号：US10108490B1

    公开(公告)日：2018-10-23

    申请号：US15604661

    申请日：2017-05-25

    Applicant: PHISON ELECTRONICS CORP.

    Inventor： Yu-Hsiang Lin ,  Shao-Wei Yen ,  Cheng-Che Yang ,  Kuo-Hsin Lai

    IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

    Abstract: A decoding method, a memory storage device and a memory control circuit unit. The method includes: reading a plurality of bits from a plurality of first memory cells; performing a first decoding operation on the bits according to first reliability information; and performing a second decoding operation on the bits according to second reliability information if the first decoding operation fails and meets a default condition, and the second reliability information is different from the first reliability information, and a correction ability of the second reliability information for a first type error of the bits is higher than a correction ability of the first reliability information for the first type error. In addition, the first type error is generated by performing a specific programming operation on the first memory cells based on error data.

    MEMORY CONTROL CIRCUIT UNIT, MEMORY STORAGE APPARATUS AND DATA ACCESSING METHOD
    40.
    发明申请
    MEMORY CONTROL CIRCUIT UNIT, MEMORY STORAGE APPARATUS AND DATA ACCESSING METHOD 有权
    存储器控制电路单元，存储器存储器和数据访问方法

    公开(公告)号：US20160266791A1

    公开(公告)日：2016-09-15

    申请号：US14702768

    申请日：2015-05-04

    Applicant: PHISON ELECTRONICS CORP.

    Inventor： Wei Lin ,  Kuo-Hsin Lai ,  Tien-Ching Wang

    IPC: G06F3/06

    CPC classification number: G06F3/0688 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G11C16/34

    Abstract: A memory control circuit unit including a plurality of data randomizer circuits and a data selection circuit is provided. When a first data stream is received from a host system, the first data stream is input into the data randomizer circuits to respectively output a plurality of second data streams. The data selection circuit selects one of the second data streams as a third data stream according to contents of the second data streams, and the third data stream is programmed into a rewritable non-volatile memory module. Accordingly, data written into the rewritable non-volatile memory module can be effectively disarranged.

    Abstract translation: 提供包括多个数据随机化器电路和数据选择电路的存储器控​​制电路单元。 当从主机系统接收到第一数据流时，将第一数据流输入到数据随机化器电路中，以分别输出多个第二数据流。 数据选择电路根据第二数据流的内容选择第二数据流中的一个作为第三数据流，并将第三数据流编程到可重写的非易失性存储器模块中。 因此，写入可重写非易失性存储器模块的数据可以被有效地排除。

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