公开(公告)号：US10076034B2

公开(公告)日：2018-09-11

申请号：US15334303

申请日：2016-10-26

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po-Chun Lin

IPC: H05K1/11 ,  H05K1/14 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H05K1/144 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03614 ,  H01L2224/0362 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/1146 ,  H01L2224/13006 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13026 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/81193 ,  H01L2224/81411 ,  H01L2224/81444 ,  H01L2225/06513 ,  H01L2225/06558 ,  H05K1/111 ,  H05K3/4015 ,  H01L2924/00014

Abstract: An electronic structure is provided. The electronic structure includes a first board structure, a first contact pad, a first joint member, and a second joint member. The first contact pad is disposed on the first board structure. The first joint member is disposed on the first contact pad, in which the first joint member has a first Young's modulus. The second joint member is disposed on the first joint member, in which the second Young's modulus has a second Young's modulus, and the second Young's modulus is greater than the first Young's modulus.

公开(公告)号：US09984995B1

公开(公告)日：2018-05-29

申请号：US15350099

申请日：2016-11-13

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po-Chun Lin

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/538 ,  H01L23/48 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5383 ,  H01L23/5385 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73257 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A semiconductor package includes a package substrate, a first semiconductor chip, a second semiconductor chip, and a top interposer. The first semiconductor chip and the second semiconductor chip are disposed on the package substrate. The top interposer is electrically connected to the first semiconductor chip and the second semiconductor chip, and the first semiconductor chip and the second semiconductor chip are present between the package substrate and the top interposer.

公开(公告)号：US09922920B1

公开(公告)日：2018-03-20

申请号：US15269974

申请日：2016-09-19

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po-Chun Lin

IPC: H01L23/48 ,  H01L23/498 ,  H01L21/48 ,  H01L21/78 ,  H01L23/00 ,  H01L25/07

CPC classification number: H01L23/49827 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/78 ,  H01L23/49838 ,  H01L24/17 ,  H01L25/072

Abstract: A method of fabricating semiconductor packages includes providing an interposer layer having a first surface and a second surface opposite to the first surface, in which the interposer layer includes through interposer vias embedded inside, and the through interposer vias extended from the first surface toward the second surface, in which through interposer vias are patterned to form repetitive polygonal-packing units, and part of the through interposer vias can be grouped within at least two distinct said polygonal-packing units; subsequently, forming at least one redistribution layer on the first surface to form terminals on a surface of the redistribution layer away from the interposer layer, in which the terminals are selectively connected to the through interposer vias respectively; and then disposing at least one semiconductor chip on the redistribution layer, wherein the semiconductor chip includes active surfaces electrically connected to the terminals respectively.

公开(公告)号：US09905549B1

公开(公告)日：2018-02-27

申请号：US15434664

申请日：2017-02-16

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po-Chun Lin ,  Chin-Lung Chu

IPC: H01L25/00 ,  H01L25/18 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L21/56 ,  H01L21/48 ,  H01L25/065

CPC classification number: H01L25/18 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49838 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/81005 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/186 ,  H01L2924/40251

Abstract: The present disclosure provides a semiconductor apparatus having a plurality of semiconductor dies stacked in a face-to-face manner and a method for preparing the same. By stacking dies having different functions vertically in a face-to-face manner, a face-to-face communication is implemented between the dies having different functions. In addition, stacking the dies having different functions vertically in a face-to-face manner reduces the occupied area of the semiconductor apparatus, as compared to a semiconductor apparatus with dies having different functions arranged in a laterally adjacent manner. Furthermore, the signal path of the dies having different functions vertically stacked in the face-to-face manner is shorter than the signal path of the dies having different functions arranged in a laterally adjacent manner; consequently, the dies having different functions vertically stacked in the face-to-face manner of the present disclosure can be applied to high-speed electronic devices.

公开(公告)号：US09786593B1

公开(公告)日：2017-10-10

申请号：US15096265

申请日：2016-04-11

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po-Chun Lin

IPC: H01L21/4763 ,  H01L21/44 ,  H01L29/40 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/5329 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13025 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01074

Abstract: A semiconductor device with a ring structure surrounding a through silicon via (TSV) electrode and a method for forming the same are disclosed. The method includes receiving a substrate including a back side and a front side having a conductor thereon, forming a via hole in the substrate and exposing the conductor, forming a groove extending from the back side into the substrate and surrounding the via hole, forming a first material layer in the via hole, and forming a second material layer in the groove. The groove filled with the second material layer forms the ring structure, while the via hole filled with the first material layer forms the TSV electrode.

公开(公告)号：US20160247777A1

公开(公告)日：2016-08-25

申请号：US15143227

申请日：2016-04-29

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po-Chun Lin

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L24/48 ,  B23K20/007 ,  B23K20/233 ,  B23K2101/42 ,  B23K2103/08 ,  B23K2103/12 ,  H01L24/45 ,  H01L24/78 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48147 ,  H01L2224/48464 ,  H01L2224/48482 ,  H01L2224/73265 ,  H01L2224/78268 ,  H01L2224/78301 ,  H01L2224/85045 ,  H01L2224/85186 ,  H01L2224/85207 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/37001 ,  H01L2924/2076 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: A wire bonding method includes the following steps. First, a substrate including at least one metal finger is provided. Next, a first chip including at least one first boding pad is disposed on the substrate. Next, a metal ball bump is foamed on the corresponding metal finger. Next, a first wire is formed from the metal ball bump toward the corresponding first boding pad. Next, a first free air ball is formed on the first wire by electronic flame-off process. Then, the first free air ball connected to the first wire is pressed on the corresponding first boding pad, such that the first wire is located between the first free air ball and the corresponding first boding pad.

Abstract translation: 引线键合方法包括以下步骤。 首先，提供包括至少一个金属指的基板。 接下来，在基板上设置包括至少一个第一编码焊盘的第一芯片。 接下来，在相应的金属手指上发泡金属球凸点。 接下来，从金属球凸块朝向相应的第一编织垫形成第一线。 接下来，通过电子熄火处理在第一线上形成第一自由空气球。 然后，连接到第一线的第一自由空气球被压在相应的第一编织垫上，使得第一线位于第一自由球和相应的第一编织垫之间。

公开(公告)号：US09362254B1

公开(公告)日：2016-06-07

申请号：US14620947

申请日：2015-02-12

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po-Chun Lin

IPC: H01L23/52 ,  H01L23/00 ,  B23K1/00

CPC classification number: H01L24/48 ,  B23K20/007 ,  B23K20/233 ,  B23K2101/42 ,  B23K2103/08 ,  B23K2103/12 ,  H01L24/45 ,  H01L24/78 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48147 ,  H01L2224/48464 ,  H01L2224/48482 ,  H01L2224/73265 ,  H01L2224/78268 ,  H01L2224/78301 ,  H01L2224/85045 ,  H01L2224/85186 ,  H01L2224/85207 ,  H01L2224/92247 ,  H01L2225/06506 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/37001 ,  H01L2924/2076 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: A wire bonding method includes the following steps. First, a substrate including at least one metal finger is provided. Next, a first chip including at least one first boding pad is disposed on the substrate. Next, a metal ball bump is formed on the corresponding metal finger. Next, a first wire is formed from the metal ball bump toward the corresponding first boding pad. Next, a first free air ball is formed on the first wire by electronic flame-off process. Then, the first free air ball connected to the first wire is pressed on the corresponding first boding pad, such that the first wire is located between the first free air ball and the corresponding first boding pad. A package structure using the wire bonding method is also provided.

Abstract translation: 引线键合方法包括以下步骤。 首先，提供包括至少一个金属指的基板。 接下来，在基板上设置包括至少一个第一编码焊盘的第一芯片。 接下来，在相应的金属指状物上形成金属球凸块。 接下来，从金属球凸块朝向相应的第一编织垫形成第一线。 接下来，通过电子熄火处理在第一线上形成第一自由空气球。 然后，连接到第一线的第一自由空气球被压在相应的第一编织垫上，使得第一线位于第一自由球和相应的第一编织垫之间。 还提供了使用引线接合方法的封装结构。