公开(公告)号：US10607858B2

公开(公告)日：2020-03-31

申请号：US16183701

申请日：2018-11-07

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po-Chun Lin ,  Chin-Lung Chu

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/482 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56 ,  H01L21/48

Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate and a first conductive bump. The semiconductor substrate has an integrated circuit and an interconnection metal layer, and a tilt surface is formed on an edge of the semiconductor substrate. The first conductive bump is electrically connected to the integrated circuit via the interconnection metal layer, and is disposed on the tilt surface, wherein a profile of the first conductive bump extends beyond a side surface of the edge of the semiconductor layer.

公开(公告)号：US10192841B2

公开(公告)日：2019-01-29

申请号：US15397044

申请日：2017-01-03

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po-Chun Lin

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56

Abstract: A semiconductor package includes a first device and a bump structure disposed over the first device. In some embodiments, the first device has a first upper surface and a first side, wherein the first upper surface and the first side form a first corner of the first device. In some embodiments, the bump structure is disposed over the first upper surface and extends laterally across the first side of the first device. The lateral extension of the bump structure across the first side of the semiconductor device can contact a corresponding conductor of a laterally adjacent device to implement a lateral signal path between the semiconductor device and the laterally adjacent device in the absence of a redistribution structure corresponding to the redistribution layer.

公开(公告)号：US10037937B2

公开(公告)日：2018-07-31

申请号：US15866483

申请日：2018-01-10

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po-Chun Lin

IPC: H01L21/4763 ,  H01L23/498 ,  H01L25/07 ,  H01L23/00 ,  H01L21/78 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/78 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/072 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2224/13099

Abstract: A method of fabricating semiconductor packages includes providing an interposer layer having a first surface and a second surface opposite to the first surface, in which the interposer layer includes through interposer vias embedded inside, and the through interposer vias extended from the first surface toward the second surface, in which through interposer vias are patterned to form repetitive polygonal-packing units, and part of the through interposer vias can be grouped within at least two distinct said polygonal-packing units; subsequently, forming at least one redistribution layer on the first surface to form terminals on a surface of the redistribution layer away from the interposer layer, in which the terminals are selectively connected to the through interposer vias respectively; and then disposing at least one semiconductor chip on the redistribution layer, wherein the semiconductor chip includes active surfaces electrically connected to the terminals respectively.

公开(公告)号：US09935071B1

公开(公告)日：2018-04-03

申请号：US15410246

申请日：2017-01-19

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po-Chun Lin ,  Chin-Lung Chu

IPC: H01L23/48 ,  H01L23/552 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L24/14 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/065 ,  H01L2224/1132 ,  H01L2224/11849 ,  H01L2224/13026 ,  H01L2224/1418 ,  H01L2224/16137

Abstract: A semiconductor package includes a semiconductor device having an upper surface and a side, wherein the upper surface and the side form a corner of the semiconductor device. The semiconductor package also includes a lateral bump structure disposed on the side and implementing a lateral signal path of the semiconductor device. The semiconductor package further includes a vertical bump structure disposed over the upper surface and implementing a vertical signal path of the semiconductor device.

公开(公告)号：US09893035B1

公开(公告)日：2018-02-13

申请号：US15345490

申请日：2016-11-07

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po-Chun Lin

IPC: H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L21/683

CPC classification number: H01L25/0652 ,  H01L21/6835 ,  H01L23/3128 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06548

Abstract: A stacked package structure includes a first package structure having a first surface and a second surface opposite to the first surface. The first package structure includes a least one first die having a first active region disposed at a bottom of the first die; a first redistribution layer disposed on the top surface of the first die; and a plurality of first bumps disposed on the bottom surface of the first active region.

公开(公告)号：US10580665B2

公开(公告)日：2020-03-03

申请号：US16203634

申请日：2018-11-29

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po-Chun Lin

IPC: H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: A package structure includes an interconnection layer; a passivation layer disposed on the interconnection layer, in which the interconnection layer and the passivation layer defined at least one opening; at least one elastic bump disposed on the interconnection layer, in which a portion of the elastic bump is embedded in the opening; and a conductive layer disposed on the elastic bump.

公开(公告)号：US10446514B2

公开(公告)日：2019-10-15

申请号：US16048357

申请日：2018-07-30

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po-Chun Lin ,  Chin-Lung Chu

IPC: H01L23/00

Abstract: A manufacturing method of a combing bump structure is disclosed. In the manufacturing method, a semiconductor substrate is provided, a pad is formed on the semiconductor substrate, a conductive layer is formed on the pad, a solder bump is formed on the conductive layer, and at least two metal side walls are formed disposed along opposing laterals of the solder bump respectively.

公开(公告)号：US10373932B2

公开(公告)日：2019-08-06

申请号：US15491995

申请日：2017-04-20

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po-Chun Lin ,  Chin-Lung Chu

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: A stacked semiconductor structure is provided. The stacked semiconductor structure includes a substrate, a first electronic component, a first fillet, and a first redistribution layer. The substrate has a support surface. The substrate includes a first pad disposed on the support surface. The first electronic component is disposed on the support surface and has a first bottom surface, a first top surface, and a first side surface connecting the first bottom surface and the first top surface. The first electronic component includes a second pad disposed on the first top surface. The first fillet is disposed on the support surface and the first side surface and has a first inclined surface. The first redistribution layer is disposed on the support surface, the first top surface, and the first inclined surface and electrically connecting the first pad to the second pad.

公开(公告)号：US10068865B1

公开(公告)日：2018-09-04

申请号：US15592181

申请日：2017-05-10

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po-Chun Lin ,  Chin-Lung Chu

IPC: H01L23/00

Abstract: A combing bump structure includes a semiconductor substrate, a pad, a conductive layer, a solder bump and at least two metal side walls The pad is disposed on the semiconductor substrate. The conductive layer is disposed on the pad. The solder bump is disposed on the conductive layer. The at least two metal side walls are disposed along opposing outer side walls of the solder bump respectively.

公开(公告)号：US09799624B1

公开(公告)日：2017-10-24

申请号：US15239809

申请日：2016-08-17

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po-Chun Lin

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L24/45 ,  H01L24/05 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/45647 ,  H01L2224/48463 ,  H01L2224/85045

Abstract: A wire bonding method includes steps of: forming a Free Air Ball (FAB) at an end of a metal wire; pressing the FAB onto a flat surface of a workpiece to deform the FAB; contacting the deformed FAB to a metal pad, wherein the metal pad is made of a first material and the metal wire is made of a second material, and a hardness of the first material is smaller than a hardness of the second material; and bonding the deformed FAB on the metal pad.