Invention Grant
- Patent Title: Stacked semiconductor structure
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Application No.: US15491995Application Date: 2017-04-20
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Publication No.: US10373932B2Publication Date: 2019-08-06
- Inventor: Po-Chun Lin , Chin-Lung Chu
- Applicant: NANYA TECHNOLOGY CORPORATION
- Applicant Address: TW New Taipei
- Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee Address: TW New Taipei
- Agency: CKC & Partners Co., LLC
- Main IPC: H01L23/00
- IPC: H01L23/00 ; H01L25/065 ; H01L25/00

Abstract:
A stacked semiconductor structure is provided. The stacked semiconductor structure includes a substrate, a first electronic component, a first fillet, and a first redistribution layer. The substrate has a support surface. The substrate includes a first pad disposed on the support surface. The first electronic component is disposed on the support surface and has a first bottom surface, a first top surface, and a first side surface connecting the first bottom surface and the first top surface. The first electronic component includes a second pad disposed on the first top surface. The first fillet is disposed on the support surface and the first side surface and has a first inclined surface. The first redistribution layer is disposed on the support surface, the first top surface, and the first inclined surface and electrically connecting the first pad to the second pad.
Public/Granted literature
- US20180308823A1 STACKED SEMICONDUCTOR STRUCTURE Public/Granted day:2018-10-25
Information query
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