公开(公告)号：US20250166687A1

公开(公告)日：2025-05-22

申请号：US18514043

申请日：2023-11-20

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WU-DER YANG

IPC: G11C11/406 ,  G11C11/408

Abstract: A memory device and a method for protecting the same are provided. The memory device includes a controller configured to refresh a first word line and a first protected word line during a first refresh cycle in response to a refresh signal, a random number generator configured to receive an address of the first word line and an address of the first protected word line to generate a first number, a counter electrically coupled to the random number generator. The counter is configured to receive the first number as an initial value of the counter, and configured to be turned on in response to the refresh signal. The controller is configured to obtain an address of a second accessed word line being accessed when the counter counts down to zero, and refresh a second protected word line, adjacent to the second accessed word line, during a second refresh cycle.

公开(公告)号：US20250158006A1

公开(公告)日：2025-05-15

申请号：US18991788

申请日：2024-12-23

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WU-DER YANG

IPC: H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/13 ,  H01L23/498 ,  H01L25/065

Abstract: A method for manufacturing a semiconductor device is provided. The method includes providing a substrate having a lower surface and an upper surface opposite to the lower surface; forming an opening extending between the upper surface and the lower surface of the substrate; attaching a first electronic component to the upper surface of the substrate, wherein an active surface of the first electronic component faces the upper surface of the substrate; attaching a second electronic component to the first electronic component, wherein an active surface of the second electronic component faces the upper surface of the substrate; and forming a bonding wire on the substrate, wherein the bonding wire passes through the opening of the substrate and electrically connects the substrate and one of the first electronic component or the second electronic component.

公开(公告)号：US20250157923A1

公开(公告)日：2025-05-15

申请号：US18508568

申请日：2023-11-14

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： CHUN-YEN WEI

IPC: H01L23/528 ,  H01L21/027 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768

Abstract: The present application discloses a cutting structure, a semiconductor device with the cutting structure, and a method for fabricating the semiconductor device. The cutting structure includes two primary cutting insulating layers positioned on two ends of a secondary cutting insulating layer and extending upwardly, wherein the two primary cutting insulating layers and the secondary cutting insulating layer together configure a U-shaped cross-sectional profile; a conductive portion positioned on the secondary cutting insulating layer and laterally surrounded by the two primary cutting insulating layers; and a capping portion positioned on the conductive portion and laterally surrounded by the two primary cutting insulating layers.

公开(公告)号：US20250149082A1

公开(公告)日：2025-05-08

申请号：US19014280

申请日：2025-01-09

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： KUO-CHIANG WANG

IPC: G11C11/4093 ,  H10B12/00 ,  H10B80/00

Abstract: A semiconductor device and a method for manufacturing a semiconductor device are provided. The semiconductor device includes a memory cell array, a memory interface, a first peripheral circuit, and a second peripheral circuit. The first peripheral circuit supports a first memory protocol, and the second peripheral circuit supports a second memory protocol different from the first memory protocol. The first peripheral circuit and the second peripheral circuit share the memory cell array and the memory interface.

公开(公告)号：US12295138B2

公开(公告)日：2025-05-06

申请号：US18369302

申请日：2023-09-18

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Liang-Pin Chou

IPC: H10B12/00

Abstract: A semiconductor device includes a plurality of drain regions in a substrate; a plurality of capacitor plugs on the plurality of drain regions; a plurality of lower electrodes on the plurality of capacitor plugs and respectively including a U-shaped cross-sectional profile; a lower supporting layer above the substrate, against on outer surfaces of the plurality of lower electrodes, and including: a plurality of first openings along the lower supporting layer and between the plurality of lower electrodes; and a higher supporting layer above the lower supporting layer, against on the outer surfaces of the plurality of lower electrodes, and including: a plurality of second openings along the higher supporting layer and topographically aligned with the plurality of first openings. The widths of the plurality of first openings and the widths of the plurality of second openings are substantially the same.

公开(公告)号：US20250133809A1

公开(公告)日：2025-04-24

申请号：US18493049

申请日：2023-10-24

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Yu Hua LIU

IPC: H01L29/51 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a semiconductor substrate and a gate structure. The semiconductor substrate has source/drain regions and a channel region between the source/drain regions. The gate structure is over the channel region of the semiconductor substrate. The gate structure includes an interfacial layer, a zirconium-containing dielectric layer, and a gate electrode. The zirconium-containing dielectric layer is over the interfacial layer and is in tetragonal-phase. The gate electrode is over the zirconium-containing dielectric layer.

公开(公告)号：US20250133777A1

公开(公告)日：2025-04-24

申请号：US18491777

申请日：2023-10-22

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Yen-Wei YEH ,  Ji-Feng LIU

IPC: H01L29/10 ,  H01L21/02 ,  H01L21/28 ,  H01L21/285 ,  H01L29/161 ,  H01L29/45 ,  H01L29/49

Abstract: A semiconductor device includes a substrate, a channel layer, a source/drain region and a gate structure. The channel layer is located on the substrate, in which the channel layer includes silicon germanium. The source/drain region is adjacent to the channel layer. The gate structure is located on the channel layer, in which the gate structure includes a dielectric layer and a work function metal layer. The dielectric layer is located on the channel layer. The work function metal layer is located on the dielectric layer.

公开(公告)号：US20250133754A1

公开(公告)日：2025-04-24

申请号：US18492451

申请日：2023-10-23

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Kai Hung LIN ,  Jyun-Hua YANG

IPC: H10B12/00

Abstract: The present disclosure provides a method of forming a capacitor. The method includes the following operations. A metal oxide insulating layer is formed on a first conductive layer with a first temperature, in which the first temperature is lower than a crystallization temperature of the metal oxide insulating layer. A second conductive layer is formed on the metal oxide insulating layer with a second temperature. An insulating layer is formed on the second conductive layer with a third temperature to crystallize the metal oxide insulating layer to form a crystallized metal oxide insulating layer, in which the second temperature is between the first temperature and the third temperature.

公开(公告)号：US20250131957A1

公开(公告)日：2025-04-24

申请号：US18520135

申请日：2023-11-27

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： WU-DER YANG

IPC: G11C11/4096

Abstract: A memory device is provided, which includes a memory cell array, a control circuit, and an interface circuit. The interface circuit includes a receiver circuit configured to amplify a first data strobe signal and a second data strobe signal received from a memory controller to generate a third data strobe signal and a fourth data strobe signal. In response to a first logic state of the first data strobe signal and a second logic state the second data strobe signal satisfying a predetermined condition, the receiver circuit adjusts a third logic state of the third data strobe signal and/or a fourth logic state of the fourth data strobe signal. The control circuit performs a write operation on the memory cell array according to the write command, the third data strobe signal, and the fourth data strobe signal.

公开(公告)号：US12284816B2

公开(公告)日：2025-04-22

申请号：US18763075

申请日：2024-07-03

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Szu-Yu Hou ,  Li-Han Lin

IPC: H10D1/68 ,  H10B12/00 ,  H10D1/00

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate having a first surface, a plurality of layers disposed on the first surface of the substrate. The plurality of layers includes a first nitride layer disposed on the first surface of the substrate, a first silicon-containing layer disposed on the first nitride layer, an intermediate nitride layer disposed on the first silicon-containing layer, a second silicon-containing layer disposed on the intermediate nitride layer, and a second nitride layer disposed on the second silicon-containing layer. In addition, the semiconductor structure includes a trench capacitor penetrating the plurality of layers and in contact with the substrate. The trench capacitor has a first portion having a first lateral surface and a second portion having a second lateral surface, and the first lateral surface has a slope different from that of the second lateral surface.