公开(公告)号：US09881937B2

公开(公告)日：2018-01-30

申请号：US15397170

申请日：2017-01-03

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Juntao Li ,  Fee Li Lie ,  Derrick Liu ,  Chun Wing Yeung

IPC: H01L27/12 ,  H01L29/66 ,  H01L21/308 ,  H01L21/84 ,  H01L29/161 ,  H01L29/78

CPC classification number: H01L27/1211 ,  H01L21/845 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7849

Abstract: A semiconductor structure includes a first strained fin portion and a second strained fin portion, a pair of inactive inner gate structures upon respective strained fin portions, and spacers upon outer sidewalls surfaces of the inactive inner gate structures, upon the inner sidewall surfaces of the inactive inner gate structures, and upon the first strained fin portion and the second strained fin portion end surfaces. The first strained fin portion and the second strained fin portion end surfaces are coplanar with respective inner sidewall surfaces of the inactive inner gate structures. The spacer formed upon the end surfaces limits relaxation of the first strained fin portion and the second strained fin portion and limits shorting between the first strained fin portion and the second strained fin portion.

公开(公告)号：US20170301770A1

公开(公告)日：2017-10-19

申请号：US15633934

申请日：2017-06-27

Applicant: International Business Machines Corporation

Inventor： Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Juntao Li ,  Fee Li Lie ,  Stuart A. Sieg ,  John R. Sporre

IPC: H01L29/66 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L29/6681 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0657 ,  H01L29/42356 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7845 ,  H01L29/7846 ,  H01L29/785

Abstract: Embodiments of the present invention provide a structure and method of minimizing stress relaxation during fin formation. Embodiments may involve forming a looped spacer on an upper surface of a substrate and adjacent to at least a sidewall of a mandrel. The mandrel may be removed, leaving the looped spacer on the substrate. An exposed portion of the substrate may be removed to form a looped fin below the looped spacer. The spacer may be removed, leaving a looped fin. A looped fin formation may reduce stress relaxation compared to conventional fin formation methods. Embodiments may include forming a gate over a looped portion of a looped fin. Securing a looped portion in position with a gate may decrease stress relaxation in the fin. Thus, a looped fin with a looped portion of the looped fin under a gate may have substantially reduced stress relaxation compared to a conventional fin.

公开(公告)号：US20170179274A1

公开(公告)日：2017-06-22

申请号：US14974537

申请日：2015-12-18

Applicant: International Business Machines Corporation

Inventor： Gauri Karve ,  Robert R. Robison ,  Reinaldo A. Vega

IPC: H01L29/78 ,  H01L29/10 ,  H01L21/225 ,  H01L29/66

CPC classification number: H01L29/66537 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0638 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/205 ,  H01L29/36 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method includes removing a top portion of a substrate after implantation of a punch through stopper into the substrate; epitaxially growing undoped material on the substrate, thereby forming a channel; filling a top portion of the channel with an intermediate implant forming a vertically bi-modal dopant distribution, with one doping concentration peak in the top portion of the channel and another doping concentration peak in the punch through stopper; and patterning fins into the channel and the punch though stopper to form a finFET structure.

公开(公告)号：US09640640B1

公开(公告)日：2017-05-02

申请号：US15135850

申请日：2016-04-22

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Fee Li Lie

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/225

CPC classification number: H01L29/66795 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for fabricating a semiconductor device, the method comprises forming a fin on a substrate, forming a dummy gate stack on the fin and the substrate, removing a portion of an exposed portion of the fin, forming a source/drain region on an exposed portion of the fin, forming a conductive contact on the source/drain region, removing the dummy gate stack to expose a channel region of the fin, implanting ions in the channel region of the fin, performing an annealing process, and forming a gate stack on the channel region of the fin.

公开(公告)号：US20170054002A1

公开(公告)日：2017-02-23

申请号：US14830969

申请日：2015-08-20

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Fee Li Lie ,  Stuart A. Sieg

IPC: H01L29/66

CPC classification number: H01L21/845 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/76213 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a layer of a second semiconductor material over the fin, the second semiconductor material operative to maintain the a strain in the strained fin, etching to remove a portion of the second semiconductor material to define a cavity that exposes a portion of the fin, etching to remove the exposed portion of the fin such that the fin is divided into a first segment and a second segment, and depositing an insulator material in the cavity, the insulator material contacting the first segment of the fin and the second segment of the fin.

Abstract translation: 一种用于在衬底上形成翅片的方法包括图案化和蚀刻第一半导体材料的层以限定应变翅片，在鳍片上沉积第二半导体材料层，第二半导体材料可操作以将应变保持在 应变翅片，蚀刻以去除第二半导体材料的一部分以限定暴露鳍片的一部分的腔，蚀刻以去除鳍的暴露部分，使得鳍分成第一段和第二段，以及 在空腔中沉积绝缘体材料，绝缘体材料接触翅片的第一段和翅片的第二段。

公开(公告)号：US20160343861A1

公开(公告)日：2016-11-24

申请号：US14719829

申请日：2015-05-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce B. Doris ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Fee Li Lie ,  Derrick Liu ,  Soon-Cheon Seo ,  Stuart A. Sieg

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.

Abstract translation: 提供一种半导体结构，其包括具有端壁并从衬底向上延伸的半导体鳍部。 栅极结构跨越半导体鳍片部分的一部分。 第一组栅极间隔物位于栅极结构的相对的侧壁表面上; 并且第二组栅极间隔物位于第一组栅极间隔物的侧壁上。 第二组栅极间隔物的一个栅极间隔物具有直接接触半导体鳍片部分的端壁的下部。

公开(公告)号：US09502411B1

公开(公告)日：2016-11-22

申请号：US14833363

申请日：2015-08-24

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Fee Li Lie ,  Stuart A. Sieg

IPC: H01L27/088 ,  H01L27/12 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/845 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/26506 ,  H01L21/30604 ,  H01L21/76213 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a layer of a second semiconductor material over the fin, the second semiconductor material operative to maintain the a strain in the strained fin, etching to remove a portion of the second semiconductor material to define a cavity that exposes a portion of the fin, etching to remove the exposed portion of the fin such that the fin is divided into a first segment and a second segment, and depositing an insulator material in the cavity, the insulator material contacting the first segment of the fin and the second segment of the fin.

Abstract translation: 一种用于在衬底上形成翅片的方法包括图案化和蚀刻第一半导体材料的层以限定应变翅片，在鳍片上沉积第二半导体材料层，第二半导体材料可操作以将应变保持在 应变翅片，蚀刻以去除第二半导体材料的一部分以限定暴露鳍片的一部分的腔，蚀刻以去除鳍的暴露部分，使得鳍分成第一段和第二段，以及 在空腔中沉积绝缘体材料，绝缘体材料接触翅片的第一段和翅片的第二段。

公开(公告)号：US11673766B2

公开(公告)日：2023-06-13

申请号：US16173781

申请日：2018-10-29

Applicant: International Business Machines Corporation

Inventor： Gauri Karve ,  Tara Astigarraga ,  Eric Miller ,  Kangguo Cheng ,  Fee Li Lie ,  Sean Teehan ,  Marc Bergendahl

IPC: B66B1/46 ,  B66B1/24 ,  B66B5/00

CPC classification number: B66B1/2458 ,  B66B1/468 ,  B66B5/0012 ,  B66B2201/103 ,  B66B2201/20 ,  B66B2201/222 ,  B66B2201/402 ,  B66B2201/403 ,  B66B2201/405 ,  B66B2201/4615 ,  B66B2201/4653 ,  B66B2201/4676

Abstract: Systems, computer-implemented methods, and computer program products that can facilitate elevator analytics and/or elevator optimization components are provided. According to an embodiment, a system can comprise a memory that stores computer executable components and a processor that executes the computer executable components stored in the memory. The computer executable components can comprise a prediction component that can predict a current destination of an elevator passenger based on historical elevator usage data of the elevator passenger. The computer executable components can further comprise an assignment component that can assign the elevator passenger to an elevator based on the current destination.

公开(公告)号：US20230055600A1

公开(公告)日：2023-02-23

申请号：US17445698

申请日：2021-08-23

Applicant: International Business Machines Corporation

Inventor： Sagarika Mukesh ,  Devika Sarkar Grant ,  FEE LI LIE ,  SHRAVAN KUMAR MATHAM ,  Hosadurga Shobha ,  Gauri Karve

IPC: H01L21/768 ,  H01L23/522

Abstract: A back-end-of-line (BEOL) component includes a substrate and a first layer of dielectric material arranged on the substrate. The first layer of dielectric material includes openings. The BEOL component further includes a first layer of metal material arranged in the openings. The BEOL component further includes an etch stop layer arranged on top of the first layer of dielectric material. The BEOL component further includes a second layer of metal material in direct contact with the first layer of metal material. The second layer of metal material includes at least one projection extending above the etch stop layer. The BEOL component further includes a second layer of dielectric material arranged on top of the etch stop layer and surrounding the at least one projection.

公开(公告)号：US11239316B2

公开(公告)日：2022-02-01

申请号：US16398999

申请日：2019-04-30

Applicant: International Business Machines Corporation

Inventor： Marc Adam Bergendahl ,  Gauri Karve ,  Fee Li Lie ,  Eric R. Miller ,  Robert Russell Robison ,  John Ryan Sporre ,  Sean Teehan

IPC: H01L21/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device includes a fin structure including a cylindrical shape, an inner gate formed inside the fin structure, and an outer gate formed outside the fin structure and connected to the inner gate.