公开(公告)号：US20170117885A1

公开(公告)日：2017-04-27

申请号：US14922072

申请日：2015-10-23

Applicant: Intel Corporation

Inventor： Daniel H. Morris ,  Uygar E. Avci ,  Ian A. Young

IPC: H03K3/356 ,  H03K3/012 ,  H01L29/66

CPC classification number: H03K3/356113 ,  H01L29/66977 ,  H03K3/012 ,  H03K3/35625

Abstract: Described is an apparatus which comprises: a first p-type Tunneling Field-Effect Transistor (TFET); a first n-type TFET coupled in series with the first p-type TFET; a first node coupled to gate terminals of the first p-type and n-type TFETs; a first clock node coupled to a source terminal of the first TFET, the first clock node is to provide a first clock; and a second clock node coupled to a source terminal of the second TFET, the second clock node is to provide a second clock.

公开(公告)号：US09570139B2

公开(公告)日：2017-02-14

申请号：US14696965

申请日：2015-04-27

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Ian A. Young

IPC: G11C11/00 ,  G11C11/16 ,  H03K19/16

CPC classification number: H01L29/66984 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1697 ,  H01L27/226 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H03K19/16

Abstract: Described is an apparatus, for spin state element device, which comprises: a variable resistive magnetic (VRM) device to receive a magnetic control signal to adjust resistance of the VRM device; and a magnetic logic gating (MLG) device, coupled to the VRM device, to receive a magnetic logic input and perform logic operation on the magnetic logic input and to drive an output magnetic signal based on the resistance of the VRM device. Described is a magnetic de-multiplexer which comprises: a first VRM device to receive a magnetic control signal to adjust resistance of the first VRM; a second VRM device to receive the magnetic control signal to adjust resistance of the second VRM device; and an MLG device, coupled to the first and second VRM devices, the MLG device having at least two output magnets to output magnetic signals based on the resistances of the first and second VRM devices.

Abstract translation: 描述了一种用于自旋状态元件器件的装置，其包括：可变电阻磁极（VRM）器件，用于接收磁控制信号以调节VRM器件的电阻; 以及耦合到VRM装置的磁逻辑门控（MLG）装置，以接收磁逻辑输入并对磁逻辑输入执行逻辑运算，并且基于VRM装置的电阻来驱动输出磁信号。 描述的磁解除多路复用器包括：第一VRM装置，用于接收磁控制信号以调整第一VRM的电阻; 第二VRM装置，用于接收所述磁控信号以调整所述第二VRM装置的电阻; 以及耦合到第一和第二VRM装置的MLG装置，MLG装置具有至少两个输出磁体，以基于第一和第二VRM装置的电阻输出磁信号。

公开(公告)号：US20160049580A1

公开(公告)日：2016-02-18

申请号：US14778704

申请日：2013-06-29

Applicant: INTEL CORPORATION

Inventor： Dmitri E. Nikonov ,  Ian A. Young

IPC: H01L43/02 ,  H01L43/12 ,  G11C11/16 ,  H01L43/08

CPC classification number: H01L43/02 ,  G11C11/161 ,  H01L43/08 ,  H01L43/12

Abstract: An embodiment includes a magnetic tunnel junction (MTJ) having a non-elliptical free layer with rounded corners. For example, an embodiment includes a MTJ including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier between the free and fixed layers; wherein the free magnetic layer includes a top surface, a bottom surface, and a sidewall circumnavigating the free magnetic layer and coupling the bottom surface to the top surface; wherein the top surface is rectangular with a plurality of rounded corners. In an embodiment, the aspect ratio of the top surface is between 4:1 and 8:1 (length to width). Such an embodiment provides ease of manufacture along with accept critical switching current (to reverse polarity of the free layer) and stability. Other embodiments are described herein.

Abstract translation: 一个实施例包括具有圆角的非椭圆形自由层的磁性隧道结（MTJ）。 例如，实施例包括在自由层和固定层之间包括自由磁性层，固定磁性层和隧道势垒的MTJ; 其中所述自由磁性层包括顶表面，底表面和环绕所述自由磁性层并将所述底表面连接到所述顶表面的侧壁; 其中所述顶表面是具有多个圆角的矩形。 在一个实施例中，顶表面的纵横比在4:1和8:1之间（长度与宽度）之间。 这样的实施例提供易于制造以及接受临界开关电流（自由层的极性反转）和稳定性。 本文描述了其它实施例。

公开(公告)号：US20250006434A1

公开(公告)日：2025-01-02

申请号：US18883126

申请日：2024-09-12

Applicant: Intel Corporation

Inventor： Chia-Ching Lin ,  Sou-Chi Chang ,  Ashish Verma Penumatcha ,  Nazila Haratipour ,  Seung Hoon Sung ,  Owen Y. Loh ,  Jack Kavalieros ,  Uygar E. Avci ,  Ian A. Young

IPC: H01G7/06 ,  H10B12/00

Abstract: Described is a ferroelectric-based capacitor that improves reliability of a ferroelectric memory by using low-leakage insulating thin film. In one example, the low-leakage insulating thin film is positioned between a bottom electrode and a ferroelectric oxide. In another example, the low-leakage insulating thin film is positioned between a top electrode and ferroelectric oxide. In yet another example, the low-leakage insulating thin film is positioned in the middle of ferroelectric oxide to reduce the leakage current and improve reliability of the ferroelectric oxide.

公开(公告)号：US11900979B2

公开(公告)日：2024-02-13

申请号：US17508818

申请日：2021-10-22

Applicant: INTEL CORPORATION

Inventor： Hai Li ,  Dmitri E. Nikonov ,  Punyashloka Debashis ,  Ian A. Young ,  Mahesh Subedar ,  Omesh Tickoo

IPC: G11C11/16 ,  G06F7/544 ,  G11C11/54 ,  G06N3/045 ,  G06N3/047

CPC classification number: G11C11/1673 ,  G06F7/5443 ,  G06N3/045 ,  G06N3/047 ,  G11C11/1675 ,  G11C11/1697 ,  G11C11/54

Abstract: Embodiments of the present disclosure are directed toward probabilistic in-memory computing configurations and arrangements, and configurations of probabilistic bit devices (p-bits) for probabilistic in-memory computing. concept with emerging. A probabilistic in-memory computing device includes an array of p-bits, where each p-bit is disposed at or near horizontal and vertical wires. Each p-bit is a time-varying resistor that has a time-varying resistance, which follows a desired probability distribution. The time-varying resistance of each p-bit represents a weight in a weight matrix of a stochastic neural network. During operation, an input voltage is applied to the horizontal wires to control the current through each p-bit. The currents are accumulated in the vertical wires thereby performing respective multiply-and-accumulative (MAC) operations. Other embodiments may be described and/or claimed.

公开(公告)号：US11769789B2

公开(公告)日：2023-09-26

申请号：US16368450

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Nazila Haratipour ,  Chia-Ching Lin ,  Sou-Chi Chang ,  Ashish Verma Penumatcha ,  Owen Loh ,  Mengcheng Lu ,  Seung Hoon Sung ,  Ian A. Young ,  Uygar Avci ,  Jack T. Kavalieros

IPC: H01G4/30 ,  H10B51/00 ,  H01L23/522 ,  H01L49/02 ,  H01G4/012

CPC classification number: H01L28/56 ,  H01G4/012 ,  H01G4/30 ,  H01L23/5226 ,  H10B51/00

Abstract: A capacitor is disclosed. The capacitor includes a first metal layer, a second metal layer on the first metal layer, a ferroelectric layer on the second metal layer, and a third metal layer on the ferroelectric layer. The second metal layer includes a first non-reactive barrier metal and the third metal layer includes a second non-reactive barrier metal. A fourth metal layer is on the third metal layer.

公开(公告)号：US11751404B2

公开(公告)日：2023-09-05

申请号：US16141025

申请日：2018-09-25

Applicant: Intel Corporation

Inventor： Abhishek Sharma ,  Gregory Chen ,  Phil Knag ,  Ram Krishnamurthy ,  Raghavan Kumar ,  Sasikanth Manipatruni ,  Amrita Mathuriya ,  Huseyin Sumbul ,  Ian A. Young

IPC: H01L27/24 ,  H10B63/00 ,  H01L29/78 ,  H01L29/66 ,  H10N70/00

CPC classification number: H10B63/30 ,  H01L29/66795 ,  H01L29/785 ,  H10N70/021 ,  H10N70/826 ,  H10N70/882 ,  H10N70/8833

Abstract: Embodiments herein describe techniques for a semiconductor device including a RRAM memory cell. The RRAM memory cell includes a FinFET transistor and a RRAM storage cell. The FinFET transistor includes a fin structure on a substrate, where the fin structure includes a channel region, a source region, and a drain region. An epitaxial layer is around the source region or the drain region. A RRAM storage stack is wrapped around a surface of the epitaxial layer. The RRAM storage stack includes a resistive switching material layer in contact and wrapped around the surface of the epitaxial layer, and a contact electrode in contact and wrapped around a surface of the resistive switching material layer. The epitaxial layer, the resistive switching material layer, and the contact electrode form a RRAM storage cell. Other embodiments may be described and/or claimed.

公开(公告)号：US20230253444A1

公开(公告)日：2023-08-10

申请号：US17666745

申请日：2022-02-08

Applicant: Intel Corporation

Inventor： Arnab Sen Gupta ,  Kaan Oguz ,  Chia-Ching Lin ,  I-Cheng Tung ,  Sudarat Lee ,  Sou-Chi Chang ,  Matthew V. Metz ,  Scott B. Clendenning ,  Uygar E. Avci ,  Ian A. Young ,  Jason C. Retasket ,  Edward O. Johnson, JR.

IPC: H01L49/02 ,  H01L27/108

CPC classification number: H01L28/65 ,  H01L28/75 ,  H01L27/10829

Abstract: Described herein are capacitor devices formed using perovskite insulators. In one example, a perovskite templating material is formed over an electrode, and a perovskite insulator layer is grown over the templating material. The templating material improves the crystal structure and electrical properties in the perovskite insulator layer. One or both electrodes may be ruthenium. In another example, a perovskite insulator layer is formed between two layers of indium tin oxide (ITO), with the ITO layers forming the capacitor electrodes.

公开(公告)号：US11626475B2

公开(公告)日：2023-04-11

申请号：US16441905

申请日：2019-06-14

Applicant: INTEL CORPORATION

Inventor： Nazila Haratipour ,  Chia-Ching Lin ,  Sou-Chi Chang ,  Ian A. Young ,  Uygar E. Avci ,  Jack T. Kavalieros

IPC: H01L21/02 ,  H01L49/02 ,  H01G4/018 ,  H01L23/64

Abstract: An improved trench capacitor structure is disclosed that allows for the formation of narrower capacitors. An example capacitor structure includes a first conductive layer on the sidewalls of an opening through a thickness of a dielectric layer, a capacitor dielectric layer on the first conductive layer, a second conductive layer on the capacitor dielectric layer, and a conductive fill material on the second conductive layer. The capacitor dielectric layer laterally extends above the opening and along a top surface of the dielectric layer, and the conductive fill material fills a remaining portion of the opening.

公开(公告)号：US11626451B2

公开(公告)日：2023-04-11

申请号：US16442767

申请日：2019-06-17

Applicant: INTEL CORPORATION

Inventor： Emily Walker ,  Carl H. Naylor ,  Kaan Oguz ,  Kevin L. Lin ,  Tanay Gosavi ,  Christopher J. Jezewski ,  Chia-Ching Lin ,  Benjamin W. Buford ,  Dmitri E. Nikonov ,  John J. Plombon ,  Ian A. Young ,  Noriyuki Sato

IPC: H01L27/22 ,  H01L43/12 ,  G11C11/16 ,  H01L43/08 ,  H01L43/02 ,  H01L43/10

Abstract: A magnetic memory device comprising a plurality of memory cells is disclosed. The memory device includes an array of memory cells where each memory cell includes a first material layer having a ferromagnetic material, a second material layer having ruthenium, and a third material layer having bismuth and/or antimony. The second material layer is sandwiched between the first material layer and the third material in a stacked configuration.