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    BURIED BIT LINE ANTI-FUSE ONE-TIME-PROGRAMMABLE NONVOLATILE MEMORY
    31.
    发明申请
    BURIED BIT LINE ANTI-FUSE ONE-TIME-PROGRAMMABLE NONVOLATILE MEMORY 有权
    BURIED BIT LINE抗保险丝一次可编程非易失性存储器

    公开(公告)号：US20100296328A1

    公开(公告)日：2010-11-25

    申请号：US12841969

    申请日：2010-07-22

    申请人： HSIANG-LAN LUNG

    发明人： HSIANG-LAN LUNG

    IPC分类号： G11C17/16

    CPC分类号： G11C17/00 ,  H01L23/5252 ,  H01L27/1021 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： An anti-fuse one-time-programmable (OTP) nonvolatile memory cell has a P well substrate with two P.sup.-doped regions. Another N.sup.+doped region, functioning as a bit line, is positioned adjacent and between the two P.sup.-doped regions on the substrate. An anti-fuse is defined over the N.sup.+doped region. Two insulator regions are deposited over the two P.sup.-doped regions. An impurity doped polysilicon layer is defined over the two insulator regions and the anti-fuse. A polycide layer is defined over the impurity doped polysilicon layer. The polycide layer and the polysilicon layer function as a word line. A programmed region, i.e., a link, functioning as a diode, is formed on the anti-fuse after the anti-fuse OTP nonvolatile memory cell is programmed. The array structure of anti-fuse OTP nonvolatile memory cells and methods for programming, reading, and fabricating such a cell are also disclosed.

    摘要翻译： 反熔丝一次可编程（OTP）非易失性存储单元具有具有两个掺杂Ps的掺杂区的P阱衬底。 用作位线的另一个N.sup +掺杂区位于衬底上的两个掺杂Ps的掺杂区之间。 在N.sup +掺杂区域上定义了反熔丝。 两个绝缘体区域沉积在两个掺杂Ps的掺杂区域上。 在两个绝缘体区域和反熔丝上限定杂质掺杂多晶硅层。 在杂质掺杂多晶硅层上限定多晶硅化物层。 多晶硅层和多晶硅层用作字线。 在反熔丝OTP非易失性存储单元被编程之后，在反熔丝上形成用作二极管的编程区域，即链路。 还公开了反熔丝OTP非易失性存储单元的阵列结构以及用于编程，读取和制造这种单元的方法。

    Phase Change Memory Cells Having Vertical Channel Access Transistor and Memory Plane
    32.
    发明申请
    Phase Change Memory Cells Having Vertical Channel Access Transistor and Memory Plane 有权
    具有垂直通道访问晶体管和存储器平面的相变存储单元

    公开(公告)号：US20100295009A1

    公开(公告)日：2010-11-25

    申请号：US12471287

    申请日：2009-05-22

    申请人： Hsiang-Lan Lung ,  Chung H. Lam ,  Ming-Hsiu Lee ,  Bipin Rajendran

    发明人： Hsiang-Lan Lung ,  Chung H. Lam ,  Ming-Hsiu Lee ,  Bipin Rajendran

    IPC分类号： H01L47/00 ,  H01L21/00

    CPC分类号： H01L27/101 ,  G11C13/0004 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675 ,  H01L45/1683

    摘要： Memory devices are described along with methods for manufacturing. A memory device as described herein comprises a plurality of word lines overlying a plurality of bit lines, and a plurality of field effect transistors. Field effect transistors in the plurality of field effect transistors comprises a first terminal electrically coupled to a corresponding bit line in the plurality of bit lines, a second terminal overlying the first terminal, and a channel region separating the first and second terminals and adjacent a corresponding word line in the plurality of word lines. The corresponding word line acts as the gate of the field effect transistor. A dielectric separates the corresponding word line from the channel region. A memory plane comprises programmable resistance memory material electrically coupled to respective second terminals of the field effect transistors, and conductive material on the programmable resistance memory material and coupled to a common voltage.

    摘要翻译： 描述存储器件以及制造方法。 如本文所述的存储器件包括覆盖多个位线的多个字线和多个场效应晶体管。 多个场效应晶体管中的场效应晶体管包括电耦合到多个位线中的对应位线的第一端子，覆盖第一端子的第二端子和分离第一和第二端子并且相邻 多行字线中的字线。 相应的字线用作场效应晶体管的栅极。 电介质将对应的字线与沟道区分开。 存储器平面包括电耦合到场效应晶体管的相应第二端子的可编程电阻存储器材料，以及可编程电阻存储器材料上的导体材料并耦合到公共电压。

    Self-align planerized bottom electrode phase change memory and manufacturing method
    35.
    发明授权
    Self-align planerized bottom electrode phase change memory and manufacturing method 有权
    自对准平面化底电极相变记忆及制造方法

    公开(公告)号：US07825396B2

    公开(公告)日：2010-11-02

    申请号：US11351296

    申请日：2006-02-09

    申请人： Hsiang-Lan Lung

    发明人： Hsiang-Lan Lung

    IPC分类号： H01L29/02

    CPC分类号： H01L45/06 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1691

    摘要： A method is described for self-aligning a bottom electrode in a phase change random access memory PCRAM device where a top electrode serves as a mask for self-aligning etching of the bottom electrode. The bottom electrode has a top surface that is planarized by chemical mechanical polishing. The top electrode also has a top surface that is planarized by chemical mechanical polishing. A bottom electrode layer like TiN is formed over a substrate and prior to the formation of a via during subsequent process steps. A first dielectric layer is formed over the bottom electrode layer, and a second dielectric layer is formed over the first dielectric layer. A via is formed at a selected section that extends through the first and second dielectric layers.

    摘要翻译： 描述了一种用于在相变随机存取存储器PCRAM器件中自对准底部电极的方法，其中顶部电极用作底部电极的自对准蚀刻的掩模。 底部电极具有通过化学机械抛光而平坦化的顶表面。 顶部电极还具有通过化学机械抛光而平坦化的顶表面。 在衬底上形成TiN的底部电极层，并且在随后的工艺步骤中形成通孔之前。 第一电介质层形成在底电极层的上方，第二电介质层形成在第一电介质层上。 通孔形成在延伸穿过第一和第二电介质层的选定部分。

    Memory structure with reduced-size memory element between memory material portions
    36.
    发明授权
    Memory structure with reduced-size memory element between memory material portions 有权
    存储器结构，在存储器材料部分之间具有减小尺寸的存储元件

    公开(公告)号：US07786461B2

    公开(公告)日：2010-08-31

    申请号：US11695667

    申请日：2007-04-03

    申请人： Hsiang-Lan Lung

    发明人： Hsiang-Lan Lung

    IPC分类号： H01L47/00

    CPC分类号： H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1666

    摘要： A memory cell device includes a memory cell access layer, a dielectric material over the memory cell access layer, a memory material structure within the dielectric material, and a top electrode in electrical contact with the memory material structure. The memory material structure has upper and lower memory material portions and a memory material element therebetween. The lower memory material layer is in electrical contact with a bottom electrode. The lower memory material layer has an average lateral dimension. The memory material element defines an electrical property state change region therein and has a minimum lateral dimension which is substantially less than the average lateral dimension. In some examples the memory material element is a tapered structure with the electrical property state change region at the junction of the memory material element and the lower memory material layer.

    摘要翻译： 存储单元器件包括存储单元访问层，存储单元访问层上的电介质材料，电介质材料内的存储材料结构以及与存储器材料结构电接触的顶电极。 记忆材料结构具有上下记忆材料部分和其间的记忆材料元件。 下部存储材料层与底部电极电接触。 较低的记忆材料层具有平均的横向尺寸。 记忆材料元件在其中限定电特性状态变化区域，并具有基本上小于平均横向尺寸的最小横向尺寸。 在一些实例中，记忆材料元件是在存储材料元件和下部存储材料层的结处具有电性能状态变化区的锥形结构。

    Buried bit line anti-fuse one-time-programmable nonvolatile memory
    37.
    发明授权
    Buried bit line anti-fuse one-time-programmable nonvolatile memory 有权
    埋地位线保险丝一次性可编程非易失性存储器

    公开(公告)号：US07786000B2

    公开(公告)日：2010-08-31

    申请号：US12557262

    申请日：2009-09-10

    申请人： Hsiang-Lan Lung

    发明人： Hsiang-Lan Lung

    IPC分类号： H01L21/425

    CPC分类号： G11C17/00 ,  H01L23/5252 ,  H01L27/1021 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： An anti-fuse one-time-programmable (OTP) nonvolatile memory cell has a P well substrate with two P.sup.− doped regions. Another N.sup.+ doped region, functioning as a bit line, is positioned adjacent and between the two P.sup.− doped regions on the substrate. An anti-fuse is defined over the N.sup.+ doped region. Two insulator regions are deposited over the two P.sup.− doped regions. An impurity doped polysilicon layer is defined over the two insulator regions and the anti-fuse. A polycide layer is defined over the impurity doped polysilicon layer. The polycide layer and the polysilicon layer function as a word line. A programmed region, i.e., a link, functioning as a diode, is formed on the anti-fuse after the anti-fuse OTP nonvolatile memory cell is programmed. The array structure of anti-fuse OTP nonvolatile memory cells and methods for programming, reading, and fabricating such a cell are also disclosed.

    摘要翻译： 反熔丝一次可编程（OTP）非易失性存储单元具有具有两个掺杂掺杂区域的P阱衬底。 作为位线起作用的另一个N.sup +掺杂区位于衬底上相邻并位于两个掺杂Ps的掺杂区之间。 在N.sup +掺杂区域上定义了反熔丝。 两个绝缘体区域沉积在两个掺杂掺杂区域上。 在两个绝缘体区域和反熔丝上限定杂质掺杂多晶硅层。 在杂质掺杂多晶硅层上限定多晶硅化物层。 多晶硅层和多晶硅层用作字线。 在反熔丝OTP非易失性存储单元被编程之后，在反熔丝上形成用作二极管的编程区域，即链路。 还公开了反熔丝OTP非易失性存储单元的阵列结构以及用于编程，读取和制造这种单元的方法。

    Memory device having wide area phase change element and small electrode contact area
    38.
    发明授权
    Memory device having wide area phase change element and small electrode contact area 有权
    具有广域相变元件和小电极接触面积的存储器件

    公开(公告)号：US07772581B2

    公开(公告)日：2010-08-10

    申请号：US11530625

    申请日：2006-09-11

    申请人： Hsiang-Lan Lung

    发明人： Hsiang-Lan Lung

    IPC分类号： H01L29/04

    CPC分类号： H01L45/06 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1675

    摘要： A memory cell device of the type that includes a memory material switchable between electrical property states by application of energy, situated between first and second (“bottom” and “top”) electrodes has a top electrode including a larger body portion and a stem portion. The memory material is disposed as a layer over a bottom electrode layer, and a base of the stem portion of the top electrode is in electrical contact with a small area of the surface of the memory material. Methods for making the memory cell are described.

    摘要翻译： 位于第一和第二（“底部”和“顶部”）电极之间的包括可通过施加能量在电性能状态之间切换的存储材料的类型的存储单元装置具有包括较大主体部分和杆部分的顶部电极 。 记忆材料被设置在底部电极层上的一层，并且顶部电极的杆部的基部与存储材料的表面的小区域电接触。 描述制造存储器单元的方法。

    Block erase for phase change memory
    39.
    发明授权
    Block erase for phase change memory 失效
    块擦除相变存储器

    公开(公告)号：US07755935B2

    公开(公告)日：2010-07-13

    申请号：US11828717

    申请日：2007-07-26

    申请人： Chung Hon Lam ,  Hsiang-Lan Lung

    发明人： Chung Hon Lam ,  Hsiang-Lan Lung

    IPC分类号： G11C11/00

    CPC分类号： G11C13/003 ,  G11C13/0004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/009 ,  G11C2213/74

    摘要： An embodiment of our invention includes a method of programming at least one phase change memory block, the at least one block comprising at least one phase change memory cell, the at least one cell comprising at least one phase change material. The method includes the steps of transitioning all cells within the at least one block to a first state and, after all cells within the at least one block have been transitioned to the first state, transitioning at least one cell within the at least one block to at least a second state. Transitioning a cell to the at least second state is faster than transitioning a cell to the first state. At least the step of transitioning all cells within the at least one block to a first state may include transitioning all cells within the at least one block in a substantially simultaneous manner.

    摘要翻译： 本发明的实施例包括编程至少一个相变存储器块的方法，所述至少一个块包括至少一个相变存储器单元，所述至少一个单元包括至少一个相变材料。 该方法包括以下步骤：将至少一个块内的所有小区转换到第一状态，并且在至少一个块内的所有小区已经转变到第一状态之后，将至少一个块内的至少一个小区转换为 至少第二状态。 将单元转换到至少第二状态比将单元转换到第一状态更快。 至少将至少一个块内的所有小区转换到第一状态的步骤可以包括以基本上同时的方式转换至少一个块内的所有小区。

    MEMORY CELL DEVICE AND PROGRAMMING METHODS
    40.
    发明申请
    MEMORY CELL DEVICE AND PROGRAMMING METHODS 有权
    存储单元设计与编程方法

    公开(公告)号：US20100157665A1

    公开(公告)日：2010-06-24

    申请号：US12715686

    申请日：2010-03-02

    申请人： Hsiang Lan Lung ,  Yi-Chou Chen

    发明人： Hsiang Lan Lung ,  Yi-Chou Chen

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0061 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0092

    摘要： A memory device including a memory cell comprising phase change material is described along with methods for programming the memory device. A method for programming disclosed herein includes determining a data value for the memory cell, and applying a pulse pair to store the data value. The pulse pair includes an initial pulse having a pulse shape adapted to preset the phase change material in the memory cell to a normalizing resistance state, and a subsequent pulse having a pulse shape adapted to set the phase change material from the normalizing resistance state to a resistance corresponding to the determined data value.

    摘要翻译： 包括包括相变材料的存储单元的存储器件与用于编程存储器件的方法一起被描述。 本文公开的编程方法包括确定存储单元的数据值，以及应用脉冲对来存储数据值。 所述脉冲对包括具有脉冲形状的初始脉冲，所述脉冲形状适于将所述存储器单元中的相变材料预设为归一化电阻状态，以及具有脉冲形状的后续脉冲，其适于将所述相变材料从所述归一化电阻状态设置为 对应于确定的数据值的电阻。