公开(公告)号：US08313979B2

公开(公告)日：2012-11-20

申请号：US13110197

申请日：2011-05-18

申请人： Hsiang-Lan Lung ,  Chung Hon Lam

发明人： Hsiang-Lan Lung ,  Chung Hon Lam

IPC分类号： H01L21/00

CPC分类号： H01L27/101 ,  G11C13/0004 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/144 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675 ,  H01L45/1683

摘要： A device includes a substrate having a first region and a second region. The first region comprises a first field effect transistor having a horizontal channel region within the substrate, a gate overlying the horizontal channel region, and a first dielectric covering the gate of the first field effect transistor. The second region of the substrate includes a second field effect transistor comprising a first terminal extending through the first dielectric to contact the substrate, a second terminal overlying the first terminal and having a top surface, and a vertical channel region separating the first and second terminals. The second field effect transistor also includes a gate on the first dielectric and adjacent the vertical channel region, the gate having a top surface that is co-planar with the top surface of the second terminal.

摘要翻译： 一种器件包括具有第一区域和第二区域的衬底。 第一区域包括在衬底内具有水平沟道区的第一场效应晶体管，覆盖在水平沟道区上的栅极和覆盖第一场效应晶体管的栅极的第一电介质。 衬底的第二区域包括第二场效应晶体管，其包括延伸穿过第一电介质以接触衬底的第一端子，覆盖第一端子并具有顶表面的第二端子和分离第一和第二端子的垂直沟道区域 。 第二场效应晶体管还包括在第一电介质上并且与垂直沟道区相邻的栅极，栅极具有与第二端子的顶表面共面的顶表面。

公开(公告)号：US08178386B2

公开(公告)日：2012-05-15

申请号：US11855983

申请日：2007-09-14

申请人： Hsiang-Lan Lung ,  Chung Hon Lam ,  Matthew J. Breitwisch

发明人： Hsiang-Lan Lung ,  Chung Hon Lam ,  Matthew J. Breitwisch

IPC分类号： H01L21/06

CPC分类号： H01L45/144 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675

摘要： An array of phase change memory cells is manufactured by forming a separation layer over an array of contacts, forming a patterning layer on the separation layer and forming an array of mask openings in the patterning layer using lithographic process. Etch masks are formed within the mask openings by a process that compensates for variation in the size of the mask openings that result from the lithographic process. The etch masks are used to etch through the separation layer to define an array of electrode openings exposing the underlying contacts. Electrode material is deposited within the electrode openings; and memory elements are formed over the bottom electrodes. Finally, bit lines are formed over the memory elements to complete the memory cells. In the resulting memory array, the critical dimension of the top surface of bottom electrode varies less than the width of the memory elements in the mask openings.

摘要翻译： 通过在触点阵列上形成分离层，在分离层上形成图形层并使用光刻工艺在图案形成层中形成掩模开口阵列来制造相变存储器单元的阵列。 通过补偿由平版印刷工艺产生的掩模开口的尺寸变化的过程，在掩模开口内形成蚀刻掩模。 蚀刻掩模用于蚀刻通过分离层以限定暴露下面的触点的电极开口的阵列。 电极材料沉积在电极开口内; 并且存储元件形成在底部电极上。 最后，在存储器元件上形成位线以完成存储器单元。 在所得到的存储器阵列中，底部电极的顶表面的临界尺寸小于掩模开口中存储元件的宽度。

公开(公告)号：US08143612B2

公开(公告)日：2012-03-27

申请号：US12621000

申请日：2009-11-18

申请人： Hsiang-Lan Lung ,  Chung Hon Lam

发明人： Hsiang-Lan Lung ,  Chung Hon Lam

IPC分类号： H01L29/06

CPC分类号： H01L45/144 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/122 ,  H01L45/1253 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1683

摘要： An array of “mushroom” style phase change memory cells is manufactured by forming a separation layer over an array of contacts, forming an isolation layer on the separation layer and forming an array of memory element openings in the isolation layer using a lithographic process. Etch masks are formed within the memory element openings by a process that compensates for variation in the size of the memory element openings that results from the lithographic process. The etch masks are used to etch through the separation layer to define an array of electrode openings. Electrode material is deposited within the electrode openings; and memory elements are formed within the memory element openings. The memory elements and bottom electrodes are self-aligned.

摘要翻译： 通过在触点阵列上形成分离层，在分离层上形成隔离层并使用光刻工艺在隔离层中形成阵列的存储元件开口来制造“蘑菇”型相变存储器单元的阵列。 通过补偿由光刻工艺产生的存储元件开口的尺寸变化的过程，在存储元件开口内形成蚀刻掩模。 蚀刻掩模用于蚀刻穿过分离层以限定电极开口的阵列。 电极材料沉积在电极开口内; 并且存储元件形成在存储元件开口内。 存储元件和底部电极是自对准的。

公开(公告)号：US08030635B2

公开(公告)日：2011-10-04

申请号：US12353219

申请日：2009-01-13

申请人： Hsiang-Lan Lung ,  Erh-Kun Lai ,  Bipin Rajendran ,  Chung Hon Lam

发明人： Hsiang-Lan Lung ,  Erh-Kun Lai ,  Bipin Rajendran ,  Chung Hon Lam

IPC分类号： H01L29/02

CPC分类号： H01L45/04 ,  G11C13/0004 ,  H01L27/1026 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/144 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675 ,  H01L45/1683

摘要： Memory devices and methods for manufacturing are described herein. A memory device described herein includes a plurality of memory cells. Memory cells in the plurality of memory cells comprise respective bipolar junction transistors and memory elements. The bipolar junction transistors are arranged in a common collector configuration and include an emitter comprising doped polysilicon having a first conductivity type, the emitter contacting a corresponding word line in a plurality of word lines to define a pn junction. The bipolar junction transistors include a portion of the corresponding word line underlying the emitter acting as a base, and a collector comprising a portion of the single-crystalline substrate underlying the base.

摘要翻译： 本文描述了存储器件和制造方法。 本文描述的存储器件包括多个存储器单元。 多个存储单元中的存储单元包括相应的双极结型晶体管和存储元件。 双极结晶体管被布置成共同的集电极配置，并且包括发射器，其包括具有第一导电类型的掺杂多晶硅，发射极与多个字线中的对应字线接触以限定pn结。 双极结晶体管包括作为基极的发射极下面的相应字线的一部分，以及包含基底下方的单晶衬底的一部分的集电极。

公开(公告)号：US07968876B2

公开(公告)日：2011-06-28

申请号：US12471301

申请日：2009-05-22

申请人： Hsiang-Lan Lung ,  Chung Hon Lam

发明人： Hsiang-Lan Lung ,  Chung Hon Lam

IPC分类号： H01L21/00

CPC分类号： H01L27/101 ,  G11C13/0004 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/144 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675 ,  H01L45/1683

摘要： Memory devices are described along with methods for manufacturing. A device as described herein includes a substrate having a first region and a second region. The first region comprises a first field effect transistor comprising first and second doped regions separated by a horizontal channel region within the substrate, a gate overlying the horizontal channel region, and a first dielectric covering the gate of the first field effect transistor. The second region of the substrate includes a second field effect transistor comprising a first terminal extending through the first dielectric to contact the substrate, a second terminal overlying the first terminal and having a top surface, and a vertical channel region separating the first and second terminals. The second field effect transistor also includes a gate on the first dielectric and adjacent the vertical channel region, the gate having a top surface that is co-planar with the top surface of the second terminal. A second dielectric separates the gate of the second field effect transistor from the vertical channel region.

摘要翻译： 描述存储器件以及制造方法。 如本文所述的器件包括具有第一区域和第二区域的衬底。 第一区域包括第一场效应晶体管，其包括由衬底内的水平沟道区域分隔的第一和第二掺杂区域，覆盖在水平沟道区域上的栅极和覆盖第一场效应晶体管的栅极的第一电介质。 衬底的第二区域包括第二场效应晶体管，其包括延伸穿过第一电介质以接触衬底的第一端子，覆盖第一端子并具有顶表面的第二端子和分离第一和第二端子的垂直沟道区域 。 第二场效应晶体管还包括在第一电介质上并且与垂直沟道区相邻的栅极，栅极具有与第二端子的顶表面共面的顶表面。 第二电介质将第二场效应晶体管的栅极与垂直沟道区分开。

公开(公告)号：US07755935B2

公开(公告)日：2010-07-13

申请号：US11828717

申请日：2007-07-26

申请人： Chung Hon Lam ,  Hsiang-Lan Lung

发明人： Chung Hon Lam ,  Hsiang-Lan Lung

IPC分类号： G11C11/00

CPC分类号： G11C13/003 ,  G11C13/0004 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/009 ,  G11C2213/74

摘要： An embodiment of our invention includes a method of programming at least one phase change memory block, the at least one block comprising at least one phase change memory cell, the at least one cell comprising at least one phase change material. The method includes the steps of transitioning all cells within the at least one block to a first state and, after all cells within the at least one block have been transitioned to the first state, transitioning at least one cell within the at least one block to at least a second state. Transitioning a cell to the at least second state is faster than transitioning a cell to the first state. At least the step of transitioning all cells within the at least one block to a first state may include transitioning all cells within the at least one block in a substantially simultaneous manner.

摘要翻译： 本发明的实施例包括编程至少一个相变存储器块的方法，所述至少一个块包括至少一个相变存储器单元，所述至少一个单元包括至少一个相变材料。 该方法包括以下步骤：将至少一个块内的所有小区转换到第一状态，并且在至少一个块内的所有小区已经转变到第一状态之后，将至少一个块内的至少一个小区转换为 至少第二状态。 将单元转换到至少第二状态比将单元转换到第一状态更快。 至少将至少一个块内的所有小区转换到第一状态的步骤可以包括以基本上同时的方式转换至少一个块内的所有小区。

公开(公告)号：US07729161B2

公开(公告)日：2010-06-01

申请号：US11833143

申请日：2007-08-02

申请人： Hsiang-Lan Lung ,  Chung Hon Lam

发明人： Hsiang-Lan Lung ,  Chung Hon Lam

IPC分类号： G11C11/00

CPC分类号： G11C13/003 ,  G11C8/08 ,  G11C8/14 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0028 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1675

摘要： A phase change memory device includes a memory cell, first word line conductor and a second word line conductor, and first and second access devices responsive to the first and second word line conductors respectively. Control circuits are arranged to access the memory cell for read operations using only the first word line conductor to establish a current path from the bit line through the memory cell to a source line through the first access device, and to access the memory cell for operations to reset the memory cell using both the first and second access devices to establish a current path from the bit line through the memory cell to two source lines.

摘要翻译： 相变存储器件包括存储单元，第一字线导体和第二字线导体，以及分别响应于第一和第二字线导体的第一和第二存取器件。 控制电路被布置为仅使用第一字线导体访问存储器单元用于读取操作，以建立从位线到存储器单元到通过第一存取设备到源极线的电流路径，以及访问存储器单元以进行操作 使用第一和第二接入设备来复位存储器单元以建立从位线到存储器单元到两条源极线的电流路径。

公开(公告)号：US20090185411A1

公开(公告)日：2009-07-23

申请号：US12017581

申请日：2008-01-22

申请人： Thomas Happ ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Bipin Rajendran ,  Min Yang

发明人： Thomas Happ ,  Chung Hon Lam ,  Hsiang-Lan Lung ,  Bipin Rajendran ,  Min Yang

IPC分类号： G11C11/00 ,  H01L21/06

CPC分类号： H01L27/24 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2213/71 ,  G11C2213/72

摘要： The integrated circuit includes a first metal line and a first diode coupled to the first metal line. The integrated circuit includes a first resistivity changing material coupled to the first diode and a second metal line coupled to the first resistivity changing material.

摘要翻译： 集成电路包括耦合到第一金属线的第一金属线和第一二极管。 集成电路包括耦合到第一二极管的第一电阻率变化材料和耦合到第一电阻率变化材料的第二金属线。

公开(公告)号：US09082954B2

公开(公告)日：2015-07-14

申请号：US13210020

申请日：2011-08-15

申请人： Hsiang-Lan Lung ,  Chung Hon Lam

发明人： Hsiang-Lan Lung ,  Chung Hon Lam

IPC分类号： G11C11/00 ,  H01L45/00

CPC分类号： H01L45/06 ,  H01L45/1246 ,  H01L45/144 ,  H01L45/16

摘要： An improved phase change memory device has a phase change structure including a thin part between a contact surface of an electrode and a dielectric structure. For example, the thin part has a maximum thickness that is smaller than a maximum width of the contact surface of the electrode. In another example, the phase change structure surrounds the dielectric structure. Several variations improve the contact between the phase change structure and an electrode.

摘要翻译： 改进的相变存储器件具有包括电极的接触表面和电介质结构之间的薄部分的相变结构。 例如，薄部具有比电极的接触表面的最大宽度小的最大厚度。 在另一示例中，相变结构围绕电介质结构。 几种变化改善了相变结构和电极之间的接触。

公开(公告)号：US08273598B2

公开(公告)日：2012-09-25

申请号：US13020051

申请日：2011-02-03

申请人： Matthew J. Breitwisch ,  Chieh-Fang Chen ,  Shih-Hung Chen ,  Eric A. Joseph ,  Chung Hon Lam ,  Michael F. Lofaro ,  Hsiang-Lan Lung ,  Alejandro G. Schrott ,  Min Yang

发明人： Matthew J. Breitwisch ,  Chieh-Fang Chen ,  Shih-Hung Chen ,  Eric A. Joseph ,  Chung Hon Lam ,  Michael F. Lofaro ,  Hsiang-Lan Lung ,  Alejandro G. Schrott ,  Min Yang

IPC分类号： H01L21/00

CPC分类号： H01L45/06 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1683

摘要： A method of forming bit line aligned to a phase change material that includes forming a pedestal of a sacrificial material on a portion of a lower electrode and forming at least one dielectric material adjacent to the sacrificial material, wherein the at least one dielectric material has an upper surface substantially coplanar with an upper surface of the pedestal of the sacrificial material. The pedestal of the sacrificial material is removed selective to the at least one dielectric material and the lower electrode to provide an opening to an exposed surface of the lower electrode. A phase change material is formed on the exposed surface of the lower electrode, and the opening is filled with a conductive fill material. A self-aligned etch back process is also provided.

摘要翻译： 一种形成与相变材料对准的位线的方法，包括在下电极的一部分上形成牺牲材料的基座并且形成与所述牺牲材料相邻的至少一个电介质材料，其中所述至少一种电介质材料具有 上表面与牺牲材料的基座的上表面基本共面。 牺牲材料的基座被选择性地移除到至少一个电介质材料和下电极以提供到下电极的暴露表面的开口。 在下电极的暴露表面上形成相变材料，并且用导电填充材料填充开口。 还提供了自对准的回蚀工艺。