Memory devices are described along with methods for manufacturing. A device as described herein includes a substrate having a first region and a second region. The first region comprises a first field effect transistor comprising first and second doped regions separated by a horizontal channel region within the substrate, a gate overlying the horizontal channel region, and a first dielectric covering the gate of the first field effect transistor. The second region of the substrate includes a second field effect transistor comprising a first terminal extending through the first dielectric to contact the substrate, a second terminal overlying the first terminal and having a top surface, and a vertical channel region separating the first and second terminals. The second field effect transistor also includes a gate on the first dielectric and adjacent the vertical channel region, the gate having a top surface that is co-planar with the top surface of the second terminal. A second dielectric separates the gate of the second field effect transistor from the vertical channel region.