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公开(公告)号：US09171613B2
公开(公告)日：2015-10-27
申请号：US13322291
申请日：2009-07-28
Applicant: Alexandre M. Bratkovski , Jianhua Yang , Shih-Yuan Wang , Michael Stuke
Inventor： Alexandre M. Bratkovski , Jianhua Yang , Shih-Yuan Wang , Michael Stuke
CPC classification number: H01L45/1273 , G11C13/0007 , G11C16/02 , G11C2213/19 , G11C2213/52 , H01L27/2463 , H01L27/2472 , H01L45/08 , H01L45/1233 , H01L45/1246 , H01L45/146 , H01L45/147 , H01L45/148
Abstract: Embodiments of the present invention are directed to nanoscale memristor devices that provide nonvolatile memristive switching. In one embodiment, a memristor device includes an active region, a first electrode disposed on a first surface of the active region, and a second electrode disposed on a second surface of the active region, the second surface opposite the first surface. The first electrode is configured with a smaller width than the active region in a first direction, and the second electrode is configured with a larger width than the active region in a second direction. Application of a voltage to at least one of the electrodes produces an electric field across a sub-region within the active region between the first electrode and the second electrode.
Abstract translation: 本发明的实施例涉及提供非易失性忆阻转换的纳米级忆阻器装置。 在一个实施例中，忆阻器件包括有源区域，设置在有源区域的第一表面上的第一电极和设置在有源区域的第二表面上的第二电极，第二表面与第一表面相对。 第一电极被配置为在第一方向上具有比有源区域更小的宽度，并且第二电极被配置为在第二方向上具有比有源区域更大的宽度。 向至少一个电极施加电压产生穿过第一电极和第二电极之间的有源区域内的子区域的电场。
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22.发明授权Methods of operating nonvolatile memory devices that support efficient error detection 有权操作支持高效错误检测的非易失性存储器件的方法公开(公告)号：US09053822B2
公开(公告)日：2015-06-09
申请号：US13777512
申请日：2013-02-26
Applicant: Ji-Sang Lee , Moosung Kim , Kihwan Choi
Inventor： Ji-Sang Lee , Moosung Kim , Kihwan Choi
CPC classification number: G11C11/5635 , G06F11/1048 , G11C11/5628 , G11C11/5642 , G11C16/02 , G11C16/0483 , G11C16/3413 , G11C16/3436 , G11C16/3454 , G11C29/04 , G11C2029/0411 , G11C2211/5621
Abstract: Methods of operating nonvolatile memory devices may include identifying one or more multi-bit nonvolatile memory cells in a nonvolatile memory device that have undergone unintentional programming from an erased state to an at least partially programmed state. Errors generated during an operation to program a first plurality of multi-bit nonvolatile memory cells may be detected by performing a plurality of reading operations to generate error detection data and then decoding the error detection data to identify specific cells having errors. A programmed first plurality of multi-bit nonvolatile memory cells and a force-bit data vector, which was modified during the program operation, may be read to support error detection. This data, along with data read from a page buffer associated with the first plurality of multi-bit nonvolatile memory cells, may then be decoded to identify which of the first plurality of multi-bit nonvolatile memory cells are unintentionally programmed cells.
Abstract translation: 操作非易失性存储器件的方法可以包括识别非易失性存储器件中的一个或多个多位非易失性存储器单元，其经历从擦除状态到至少部分编程状态的无意编程。 可以通过执行多个读取操作来生成错误检测数据，然后解码错误检测数据以识别具有错误的特定单元，来检测在编程第一多个多位非易失性存储器单元的操作期间产生的错误。 可以读取编程的第一多个多位非易失性存储单元和在编程操作期间被修改的强位数据向量，以支持错误检测。 然后可以将该数据连同从与第一多个多位非易失性存储器单元相关联的页面缓冲器读取的数据解码以识别第一多个多位非易失性存储器单元中的哪一个是无意编程的单元。
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公开(公告)号：US20130322171A1
公开(公告)日：2013-12-05
申请号：US13777512
申请日：2013-02-26
Applicant: Ji-Sang Lee , Moosung Kim , Kihwan Choi
Inventor： Ji-Sang Lee , Moosung Kim , Kihwan Choi
CPC classification number: G11C11/5635 , G06F11/1048 , G11C11/5628 , G11C11/5642 , G11C16/02 , G11C16/0483 , G11C16/3413 , G11C16/3436 , G11C16/3454 , G11C29/04 , G11C2029/0411 , G11C2211/5621
Abstract: Methods of operating nonvolatile memory devices may include identifying one or more multi-bit nonvolatile memory cells in a nonvolatile memory device that have undergone unintentional programming from an erased state to an at least partially programmed state. Errors generated during an operation to program a first plurality of multi-bit nonvolatile memory cells may be detected by performing a plurality of reading operations to generate error detection data and then decoding the error detection data to identify specific cells having errors. A programmed first plurality of multi-bit nonvolatile memory cells and a force-bit data vector, which was modified during the program operation, may be read to support error detection. This data, along with data read from a page buffer associated with the first plurality of multi-bit nonvolatile memory cells, may then be decoded to identify which of the first plurality of multi-bit nonvolatile memory cells are unintentionally programmed cells.
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公开(公告)号：US20130258779A1
公开(公告)日：2013-10-03
申请号：US13993312
申请日：2011-09-22
Applicant: Zengtao Liu
Inventor： Zengtao Liu
IPC: G11C16/02
CPC classification number: H01L27/11565 , G11C16/02 , H01L27/1157 , H01L27/11573 , H01L27/11582
Abstract: Embodiments of the present disclosure describe methods, apparatus, and system configurations for NAND memory arrays with mis-matched cell and bitline pitch. Other embodiments may be described and claimed.
Abstract translation: 本公开的实施例描述了具有错误匹配的单元和位线间距的NAND存储器阵列的方法，装置和系统配置。 可以描述和要求保护其他实施例。
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公开(公告)号：US20120314495A1
公开(公告)日：2012-12-13
申请号：US13588196
申请日：2012-08-17
Applicant: Gerrit Jan Hemink
Inventor： Gerrit Jan Hemink
CPC classification number: G11C16/3418 , G11C16/3427
Abstract: The unintentional programming of an unselected (or inhibited) non-volatile storage element during a program operation that intends to program another non-volatile storage element is referred to as “program disturb.” A system is proposed for programming and/or reading non-volatile storage that reduces the effect of program disturb. In one embodiment, different verify levels are used for a particular word line (or other grouping of storage elements) during a programming process. In another embodiment, different compare levels are used for a particular word (or other grouping of storage elements) during a read process.
Abstract translation: 在期望编程另一非易失性存储元件的程序操作期间未选择（或禁止）非易失性存储元件的无意编程被称为程序干扰。 提出了一种用于编程和/或读取非易失性存储器的系统，其减少了编程干扰的影响。 在一个实施例中，在编程过程期间，对于特定字线（或存储元件的其他分组）使用不同的验证电平。 在另一个实施例中，在读取过程期间，不同的比较级别用于特定单词（或存储单元的其他分组）。
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Patent Agency Ranking
公开(公告)号：US08151060B2
公开(公告)日：2012-04-03
申请号：US11783364
申请日：2007-04-09
Applicant: Nagamasa Mizushima
Inventor： Nagamasa Mizushima
CPC classification number: G06F12/0246 , G06F11/1415 , G06F11/1471 , G06F12/1009 , G06F2201/84
Abstract: In a semiconductor memory computer equipped with a flash memory, use of backed-up data is enabled. The semiconductor memory computer includes an address conversion table for detecting physical addresses of at least two pages storing data by designating a logical address from one of logical addresses to be designated by a reading request. The semiconductor memory computer includes a page status register for detecting one page status allocated to each page, and page statuses to be detected include the at least following four statuses: (1) a latest data storage status, (2) a not latest data storage status, (3) an invalid data storage status, and (4) an unwritten status. By using the address conversion table and the page status register, at least two data s (latest data and past data) can be read for one designated logical address from a host computer.
Abstract translation: 在配有闪存的半导体存储器中，使用备份数据。 半导体存储器计算机包括地址转换表，用于通过从由读取请求指定的逻辑地址之一指定逻辑地址来检测存储数据的至少两个页面的物理地址。 半导体存储器计算机包括用于检测分配给每个页面的一页状态的页面状态寄存器，并且要检测的页面状态包括至少以下四个状态：（1）最新数据存储状态，（2）不是最新的数据存储 状态，（3）无效数据存储状态，以及（4）不成文状态。 通过使用地址转换表和页面状态寄存器，可以从主机为一个指定的逻辑地址读取至少两个数据s（最新数据和过去数据）。
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公开(公告)号：US08094496B2
公开(公告)日：2012-01-10
申请号：US12475799
申请日：2009-06-01
Applicant: Akira Umezawa
Inventor： Akira Umezawa
CPC classification number: G11C16/10 , G11C16/0466 , H01L21/28282 , H01L27/11568 , H01L29/42352 , H01L29/66833 , H01L29/792
Abstract: A nonvolatile semiconductor memory device includes a multi-layer insulating film having at least charge storage layers and formed on bottom surfaces and both side surfaces of a plurality of trench portions respectively formed in portions between the plurality of active areas formed in a first direction, a plurality of gate electrodes filled in internal portions of the plurality of trench portions with the multi-layer insulating film, a plurality of first metal interconnections formed in a second direction and each functioning as a bit line or source line, and a plurality of first conductivity-type diffusion layer regions arranged in a staggered form in corresponding portions of the plurality of active areas which intersect with the plurality of first metal interconnections. The device further includes a plurality of connection contacts form to respectively connect the plurality of first conductivity-type diffusion layer regions to the plurality of first metal interconnections.
Abstract translation: 非易失性半导体存储器件包括至少具有电荷存储层并且形成在分别形成在沿第一方向形成的多个有源区域之间的部分中的多个沟槽部分的底表面和两个侧表面上的多层绝缘膜， 多个栅电极，多个沟槽部的内部被多层绝缘膜填充，多个第一金属互连形成在第二方向上，并且各自作为位线或源极线，以及多个第一导电性 型扩散层区域以交错的形式布置在与多个第一金属互连相交的多个有效区域的对应部分中。 该装置还包括多个连接触头形式，以将多个第一导电类型扩散层区域分别连接到多个第一金属互连。
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公开(公告)号：US20110242894A1
公开(公告)日：2011-10-06
申请号：US12755220
申请日：2010-04-06
Applicant: ANDREW W. VOGAN
Inventor： ANDREW W. VOGAN
CPC classification number: G11C29/883
Abstract: A method and system to facilitate the usage of memory modules that have one or more defective memory dies. In one embodiment of the invention, a memory module is packaged with a number of dies and the memory module is tested and sorted according to the number of dies that pass testing. Each signal of each die in the memory module has an unique bond-out or connection point in the package of the memory module. By separating the signals of each die in the memory module, any defective die can be easily isolated and this allows a significant cost reduction in products that use a large number of dies.
Abstract translation: 一种促进使用具有一个或多个缺陷存储器管芯的存储器模块的方法和系统。 在本发明的一个实施例中，存储器模块与多个管芯一起封装，并且根据通过测试的管芯的数量对存储器模块进行测试和分类。 存储器模块中每个芯片的每个信号在存储器模块的封装中具有唯一的键合或连接点。 通过分离存储器模块中的每个管芯的信号，可以容易地隔离任何有缺陷的管芯，并且这允许在使用大量管芯的产品中显着降低成本。
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公开(公告)号：US20110235417A1
公开(公告)日：2011-09-29
申请号：US13154522
申请日：2011-06-07
Applicant: Katsuaki Isobe
Inventor： Katsuaki Isobe
IPC: G11C16/02
CPC classification number: G11C8/08 , G11C8/10 , G11C16/0483
Abstract: A NAND flash memory that is read while a selected bit line and a non-selected bit line are adjacent to each other, has a memory cell array having a plurality of blocks each of which is composed of a plurality of memory cell units, each of said memory cell units having a plurality of electrically rewritable memory cells that are connected to each other and composed of a p-type well surrounded by an n-type well formed in a p-type semiconductor substrate, drain-side select gate transistors each of which connects a memory cell unit to a bit line and is connected to a drain-side select gate line at the gate thereof, and source-side select gate transistors each of which connects a memory cell unit to a source line and is connected to a source-side select gate line at the gate thereof; a row decoder that is connected to word lines, the drain-side select gate lines and the source-side gate line of said memory cell array, and applies a signal voltage to word lines, the drain-side select gate lines and the source-side gate line of said memory cell array for selecting a block; and a sense amplifier that is controlled by a column decoder and makes a selection from said bit lines of said memory cell array, wherein, in a block that is not selected by said row decoder, said bit line selected by said sense amplifier is charged in a state where the drain-side select gate line, the source-side select gate line and the p-type semiconductor substrate are set at a ground potential, and the source lines, the n-type wells, the p-type wells and a bit line that is not selected by said sense amplifier are in a floating state.
Abstract translation: 在选择的位线和非选择的位线彼此相邻时读取的NAND快闪存储器具有存储单元阵列，其具有多个块，每个块由多个存储单元单元组成，每个块由多个存储单元单元组成 所述存储单元具有多个电可重写存储单元，它们彼此连接并且由形成在p型半导体衬底中的n型阱围绕的p型阱组成，每个漏极侧选择栅晶体管 其将存储单元单元连接到位线并连接到其栅极处的漏极侧选择栅极线，以及源极选择栅极晶体管，每个源极选择栅极晶体管将存储单元单元连接到源极线并连接到 源极选择栅极线; 连接到所述存储单元阵列的字线，漏极侧选择栅极线和源极侧栅极线的行解码器，并将信号电压施加到字线，漏极侧选择栅极线和源极侧选择栅极线， 所述存储单元阵列的侧栅极线用于选择块; 以及由列解码器控制并从所述存储单元阵列的所述位线进行选择的读出放大器，其中，在未被所述行解码器选择的块中，由所述读出放大器选择的所述位线被充电 漏极侧选择栅极线，源极侧选择栅极线和p型半导体衬底设置为接地电位的状态，源极线，n型阱，p型阱和a 未被所述读出放大器选择的位线处于浮置状态。
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公开(公告)号：US20110051527A1
公开(公告)日：2011-03-03
申请号：US12725827
申请日：2010-03-17
Applicant: Ryouhei Kirisawa , Masaru Kito , Shigeto Oota , Yoshimasa Mikajiri
Inventor： Ryouhei Kirisawa , Masaru Kito , Shigeto Oota , Yoshimasa Mikajiri
CPC classification number: G11C16/14 , G11C16/0483 , G11C16/10 , G11C16/26 , H01L27/11582
Abstract: A nonvolatile semiconductor memory device includes: a memory unit; and a control unit. The memory unit includes: first and second memory strings including first and second memory transistors with first and second select gates, respectively; and first and second wirings connected thereto. In a selective erase operation of a selected cell transistor of the first memory transistors, the control unit applies V1 voltage to the first wiring, applies V2 voltage lower than V1 to a selected cell gate of the selected cell transistor, applies V3 voltage not higher than V1 and higher than V2 to a non-selected cell gate of the first memory transistors, applies V1 or V4 voltage not higher than V1 and not lower than V3 to the first select gate, and applies V2 or V4 voltage higher than V2 and not higher than V3 to the second wiring or sets the second wiring in a floating state.
Abstract translation: 非易失性半导体存储器件包括：存储器单元; 和控制单元。 存储单元包括：第一和第二存储器串，分别包括具有第一和第二选择栅极的第一和第二存储器晶体管; 以及与其连接的第一和第二布线。 在第一存储晶体管的所选单元晶体管的选择性擦除操作中，控制单元向第一布线施加V1电压，向所选单元晶体管的选定单元栅极施加低于V1的V2电压，施加不高于 V1并且高于V2到第一存储晶体管的未选择的单元栅极，向第一选择栅施加不高于V1且不低于V3的V1或V4电压，并且施加V2或V4电压高于V2而不是更高 而不是V3到第二布线，或将第二布线置于浮置状态。
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