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Invention Application
US20130258779A1 NAND MEMORY ARRAY WITH MISMATCHED CELL AND BITLINE PITCH 有权
NAND存储器阵列与错配单元和位线PITCH

  • Patent Title: NAND MEMORY ARRAY WITH MISMATCHED CELL AND BITLINE PITCH
  • Patent Title (中): NAND存储器阵列与错配单元和位线PITCH
  • Application No.: US13993312
    Application Date: 2011-09-22
  • Publication No.: US20130258779A1
    Publication Date: 2013-10-03
  • Inventor: Zengtao Liu
  • Applicant: Zengtao Liu
  • International Application: PCT/US2011/052846 WO 20110922
  • Main IPC: G11C16/02
  • IPC: G11C16/02
NAND MEMORY ARRAY WITH MISMATCHED CELL AND BITLINE PITCH
Abstract:
Embodiments of the present disclosure describe methods, apparatus, and system configurations for NAND memory arrays with mis-matched cell and bitline pitch. Other embodiments may be described and claimed.
Abstract(Chinese):

本公开的实施例描述了具有错误匹配的单元和位线间距的NAND存储器阵列的方法，装置和系统配置。 可以描述和要求保护其他实施例。

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