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    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    2.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
    非易失性半导体存储器件

    公开(公告)号：US20110051527A1

    公开(公告)日：2011-03-03

    申请号：US12725827

    申请日：2010-03-17

    Applicant: Ryouhei Kirisawa ,  Masaru Kito ,  Shigeto Oota ,  Yoshimasa Mikajiri

    Inventor： Ryouhei Kirisawa ,  Masaru Kito ,  Shigeto Oota ,  Yoshimasa Mikajiri

    IPC: G11C16/04 ,  G11C16/02

    CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  H01L27/11582

    Abstract: A nonvolatile semiconductor memory device includes: a memory unit; and a control unit. The memory unit includes: first and second memory strings including first and second memory transistors with first and second select gates, respectively; and first and second wirings connected thereto. In a selective erase operation of a selected cell transistor of the first memory transistors, the control unit applies V1 voltage to the first wiring, applies V2 voltage lower than V1 to a selected cell gate of the selected cell transistor, applies V3 voltage not higher than V1 and higher than V2 to a non-selected cell gate of the first memory transistors, applies V1 or V4 voltage not higher than V1 and not lower than V3 to the first select gate, and applies V2 or V4 voltage higher than V2 and not higher than V3 to the second wiring or sets the second wiring in a floating state.

    Abstract translation: 非易失性半导体存储器件包括：存储器单元; 和控制单元。 存储单元包括：第一和第二存储器串，分别包括具有第一和第二选择栅极的第一和第二存储器晶体管; 以及与其连接的第一和第二布线。 在第一存储晶体管的所选单元晶体管的选择性擦除操作中，控制单元向第一布线施加V1电压，向所选单元晶体管的选定单元栅极施加低于V1的V2电压，施加不高于 V1并且高于V2到第一存储晶体管的未选择的单元栅极，向第一选择栅施加不高于V1且不低于V3的V1或V4电压，并且施加V2或V4电压高于V2而不是更高 而不是V3到第二布线，或将第二布线置于浮置状态。

    Nonvolatile semiconductor memory device and method for producing same
    4.
    发明授权
    Nonvolatile semiconductor memory device and method for producing same 失效
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US06555870B1

    公开(公告)日：2003-04-29

    申请号：US09605895

    申请日：2000-06-29

    Applicant: Ryouhei Kirisawa

    Inventor： Ryouhei Kirisawa

    IPC: H01L29792

    CPC classification number: H01L29/7926 ,  G11C16/0491 ,  H01L27/115 ,  H01L27/11553 ,  H01L27/11556 ,  H01L29/7886 ,  H01L29/792

    Abstract: A groove 11 is formed in a semiconductor substrate 10. A source region 12 is formed on the bottom of the groove 11 on the side of the surface of the semiconductor substrate 10. A drain region 14 is formed in a portion, in which the groove 11 is not formed, on the side of the surface of the semiconductor substrate 10. Floating gates 30 are formed on both inner side wall portions of the groove 11 as charge storage layers. By thus three-dimensionally forming a memory transistor, it is possible to achieve the high density integration of a nonvolatile semiconductor memory device.

    Abstract translation: 沟槽11形成在半导体衬底10中。源极区12形成在半导体衬底10的表面侧上的沟槽11的底部。漏区14形成在凹槽11的一部分中， 11不形成在半导体基板10的表面侧上。浮动栅极30形成在槽11的两个内侧壁部分上，作为电荷存储层。 通过这样三维形成存储晶体管，可以实现非易失性半导体存储器件的高密度集成。

    Electrically erasable and programmable non-volatile memory system with write-verify controller using two reference levels
    5.
    发明授权
    Electrically erasable and programmable non-volatile memory system with write-verify controller using two reference levels 失效
    具有写入验证控制器的电可擦除和可编程非易失性存储器系统，使用两个参考电平

    公开(公告)号：US5321699A

    公开(公告)日：1994-06-14

    申请号：US851286

    申请日：1992-03-12

    Applicant: Tetsuo Endoh ,  Riichiro Shirota ,  Kazunori Ohuchi ,  Ryouhei Kirisawa ,  Seiichi Aritome ,  Tomoharu Tanaka ,  Yoshiyuki Tanaka

    Inventor： Tetsuo Endoh ,  Riichiro Shirota ,  Kazunori Ohuchi ,  Ryouhei Kirisawa ,  Seiichi Aritome ,  Tomoharu Tanaka ,  Yoshiyuki Tanaka

    IPC: G11C11/56 ,  G11C16/34 ,  G11C29/50 ,  G01R31/28

    CPC classification number: G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/3404 ,  G11C16/3413 ,  G11C16/3418 ,  G11C16/3431 ,  G11C16/3459 ,  G11C29/50 ,  G06F2201/81 ,  G11C16/04 ,  G11C2029/0403 ,  G11C2211/5621

    Abstract: An EEPROM includes an array of memory cell transistors, which is divided into cell blocks each including NAND cell units of series-connected cell transistors. A sense amplifier is connected to bit lines and a comparator. A data-latch circuit is connected to the comparator, for latching a write-data supplied from a data input buffer. After desired cell transistors selected for programming in a selected block are once programmed, a write-verify operation is performed. The comparator compares the actual data read from one of the programmed cell transistors with the write-data, to verify its written state. The write-verify process checks the resulting threshold voltage for variations using first and second reference voltages defining the lower-limit and upper-limit of an allowable variation range. If the comparison results under employment of the first voltage shows that an irregularly written cell transistor remains with an insufficient threshold voltage which is so low as to fail to fall within the range, the write operation continues for the same cell transistor. If the comparison results under employment of the second voltage shows that an excess-written cell transistor remains, the block is rendered "protected" at least partially.

    Abstract translation: EEPROM包括存储单元晶体管的阵列，其被分成每个包括串联连接的单元晶体管的NAND单元单元的单元块。 读出放大器连接到位线和比较器。 数据锁存电路连接到比较器，用于锁存从数据输入缓冲器提供的写入数据。 在所选择的块中选择用于编程的所需单元晶体管被一次编程之后，执行写验证操作。 比较器将从编程单元晶体管之一读取的实际数据与写入数据进行比较，以验证其写入状态。 写验证过程使用限定允许变化范围的下限和上限的第一和第二参考电压来检查所得到的阈值电压的变化。 如果使用第一电压的比较结果表明，不规则写入的单元晶体管保持不足阈值电压，其不足以落在该范围内，对于相同的单元晶体管，写操作继续进行。 如果在使用第二电压的情况下的比较结果表明剩余写入过多的单元晶体管，则该块至少部分地被“保护”。

    Nonvolatile semiconductor memory device and manufacturing method thereof
    8.
    发明授权
    Nonvolatile semiconductor memory device and manufacturing method thereof 失效
    非易失性半导体存储器件及其制造方法

    公开(公告)号：US08581326B2

    公开(公告)日：2013-11-12

    申请号：US12727644

    申请日：2010-03-19

    Applicant: Shigeto Oota ,  Yoshimasa Mikajiri ,  Ryouhei Kirisawa

    Inventor： Shigeto Oota ,  Yoshimasa Mikajiri ,  Ryouhei Kirisawa

    IPC: H01L29/788 ,  H01L21/336

    CPC classification number: H01L29/792 ,  H01L27/11578 ,  H01L27/11582 ,  H01L27/1203 ,  H01L29/66833 ,  H01L29/7926

    Abstract: A nonvolatile semiconductor memory device including first laminated bodies each having a plurality of first gate electrodes of first memory cells, second laminated bodies each having a plurality of second gate electrodes of second memory cells, gate insulating film portions located on side surfaces of the first and second laminated bodies, first semiconductor layers that are each located between the first and second laminated bodies, first select transistors connected to an uppermost one of the first memory cells, second select transistors connected to an uppermost one of the second memory cells, isolation insulating films to separate the first and second select transistors into portions on the first and second laminated body sides, and a substrate potential applying electrode located to penetrate the isolation insulating films from a front surface side to a back surface side and connected to the first semiconductor layers.

    Abstract translation: 一种非易失性半导体存储器件，包括：第一层叠体，其具有第一存储单元的多个第一栅电极;第二层叠体，每个第二层叠体具有第二存储单元的多个第二栅电极，位于第一存储单元的侧表面的栅绝缘膜部; 第二层叠体，各自位于第一和第二层叠体之间的第一半导体层，连接到第一存储单元中的最上面的第一选择晶体管，连接到第二存储单元中最上面的第一选择晶体管，隔离绝缘膜 将第一和第二选择晶体管分离成第一和第二层叠体侧的部分，以及位于从前表面侧到背面侧穿透隔离绝缘膜并连接到第一半导体层的衬底电位施加电极。

    Nonvolatile semiconductor memory device
    10.
    发明授权
    Nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件

    公开(公告)号：US08320182B2

    公开(公告)日：2012-11-27

    申请号：US12725827

    申请日：2010-03-17

    Applicant: Ryouhei Kirisawa ,  Masaru Kito ,  Shigeto Oota ,  Yoshimasa Mikajiri

    Inventor： Ryouhei Kirisawa ,  Masaru Kito ,  Shigeto Oota ,  Yoshimasa Mikajiri

    IPC: G11C11/34 ,  G11C16/04

    CPC classification number: G11C16/14 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  H01L27/11582

    Abstract: A nonvolatile semiconductor memory device includes: a memory unit; and a control unit. The memory unit includes: first and second memory strings including first and second memory transistors with first and second select gates, respectively; and first and second wirings connected thereto. In a selective erase operation of a selected cell transistor of the first memory transistors, the control unit applies V1 voltage to the first wiring, applies V2 voltage lower than V1 to a selected cell gate of the selected cell transistor, applies V3 voltage not higher than V1 and higher than V2 to a non-selected cell gate of the first memory transistors, applies V1 or V4 voltage not higher than V1 and not lower than V3 to the first select gate, and applies V2 or V4 voltage higher than V2 and not higher than V3 to the second wiring or sets the second wiring in a floating state.

    Abstract translation: 非易失性半导体存储器件包括：存储器单元; 和控制单元。 存储单元包括：第一和第二存储器串，分别包括具有第一和第二选择栅极的第一和第二存储器晶体管; 以及与其连接的第一和第二布线。 在第一存储晶体管的所选单元晶体管的选择性擦除操作中，控制单元向第一布线施加V1电压，向所选单元晶体管的选定单元栅极施加低于V1的V2电压，施加不高于 V1并且高于V2到第一存储晶体管的未选择的单元栅极，向第一选择栅施加不高于V1且不低于V3的V1或V4电压，并且施加V2或V4电压高于V2而不是更高 而不是V3到第二布线，或将第二布线置于浮置状态。

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