知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

137 records (took 0.034 seconds)

    Non-volatile memory and methods with soft-bit reads while reading hard bits with compensation for coupling
    1.
    发明授权
    Non-volatile memory and methods with soft-bit reads while reading hard bits with compensation for coupling 有权
    非易失性存储器和具有软位读取的方法，同时读取具有补偿补偿的硬比特

    公开(公告)号：US08498152B2

    公开(公告)日：2013-07-30

    申请号：US12978368

    申请日：2010-12-23

    Applicant: Idan Alrod ,  Eran Sharon ,  Toru Miwa ,  Gerrit Jan Hemink ,  Nima Mokhlesi

    Inventor： Idan Alrod ,  Eran Sharon ,  Toru Miwa ,  Gerrit Jan Hemink ,  Nima Mokhlesi

    IPC: G11C11/34

    CPC classification number: G11C16/34 ,  G06F11/1072 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/3422 ,  G11C16/3427 ,  G11C29/00

    Abstract: A non-volatile memory has its cells' thresholds programmed within any one of a first set of voltage bands partitioned by a first set of reference thresholds across a threshold window. Hard bits are obtained when read relative to the first set of reference thresholds. The cells are read at a higher resolution relative to a second set of reference thresholds so as to provide additional soft bits for error correction. The soft bits are generated by a combination of a first modulation of voltage on a current word line WLn and a second modulation of voltage on an adjacent word line WLn+1, as in a reading scheme known as “Direct-Lookahead (DLA)”.

    Abstract translation: 非易失性存储器的单元的阈值被编程在跨越阈值窗口的第一组参考阈值划分的第一组电压带的任一个中。 当读取相对于第一组参考阈值时，获得硬比特。 相对于第二组参考阈值以更高的分辨率读取单元，以便提供用于纠错的附加软比特。 软位是通过对当前字线WLn上的电压的第一次调制和相邻字线WLn + 1上的电压的第二调制的组合产生的，如在称为“直读先锋（DLA）”的读取方案中 。

    Detecting the completion of programming for non-volatile storage
    2.
    发明授权
    Detecting the completion of programming for non-volatile storage 有权

    公开(公告)号：US08416626B2

    公开(公告)日：2013-04-09

    申请号：US13237814

    申请日：2011-09-20

    Applicant: Gerrit Jan Hemink

    Inventor： Gerrit Jan Hemink

    IPC: G11C11/34

    CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/3454

    Abstract: A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target condition to store the appropriate data. Programming can be stopped when all non-volatile storage elements have reached their target level or when the number of non-volatile storage elements that have not reached their target level is less than a number or memory cells that can be corrected using an error correction process during a read operation (or other operation). The number of non-volatile storage elements that have not reached their target level can be estimated by counting the number of non-volatile storage elements that have not reached a condition that is different (e.g., lower) than the target level.

    Ramping Pass Voltage To Enhance Channel Boost In Memory Device, With Optional Temperature Compensation
    3.
    发明申请
    Ramping Pass Voltage To Enhance Channel Boost In Memory Device, With Optional Temperature Compensation 有权
    缓存通过电压，以增强存储器件中的通道升压，具有可选的温度补偿

    公开(公告)号：US20120300550A1

    公开(公告)日：2012-11-29

    申请号：US13113786

    申请日：2011-05-23

    Applicant: Gerrit Jan Hemink ,  Shih-Chung Lee ,  Anubhav Khandelwal ,  Henry Chin ,  Guirong Liang ,  Dana Lee

    Inventor： Gerrit Jan Hemink ,  Shih-Chung Lee ,  Anubhav Khandelwal ,  Henry Chin ,  Guirong Liang ,  Dana Lee

    IPC: G11C16/04

    CPC classification number: G11C16/3427 ,  G11C16/10

    Abstract: In a non-volatile storage system, one or more substrate channel regions for an unselected NAND string are boosted during programming to inhibit program disturb. A voltage applied to one or more unselected word lines associated with at least a first channel region is increased during a program pulse time period in which a program pulse is applied to a selected word line. The increase can be gradual, in the form of a ramp, or step-wise. The boosting level of the first channel region can be maintained. The increase in the voltage applied to the one or more unselected word lines can vary with temperature as well. Before the program pulse time period, the voltage applied to the one or more unselected word lines can be ramped up at a faster rate for a second, adjacent channel region than for the first channel region, to help isolate the channel regions.

    Abstract translation: 在非易失性存储系统中，用于未选择的NAND串的一个或多个衬底沟道区在编程期间升高以抑制编程干扰。 在将编程脉冲施加到所选字线的编程脉冲时间段期间，施加到与至少第一信道区域相关联的一个或多个未选择字线的电压增加。 增加可以是渐进的，以斜坡的形式，或逐步的。 可以维持第一通道区域的升压水平。 施加到一个或多个未选择字线的电压的增加也随着温度而变化。 在编程脉冲时间段之前，施加到一个或多个未选择字线的电压可以以比第一通道区域更快的速率向第二相邻通道区域上升，以帮助隔离通道区域。

    Programming non-volatile memory with high resolution variable initial programming pulse
    4.
    发明授权
    Programming non-volatile memory with high resolution variable initial programming pulse 有权
    用高分辨率可编程初始编程脉冲编程非易失性存储器

    公开(公告)号：US08223554B2

    公开(公告)日：2012-07-17

    申请号：US13237755

    申请日：2011-09-20

    Applicant: Gerrit Jan Hemink

    Inventor： Gerrit Jan Hemink

    IPC: G11C11/34

    CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3468 ,  G11C16/3486 ,  G11C2211/5621 ,  G11C2211/5648

    Abstract: Each of the programming processes operate to program at least a subset of the non-volatile storage elements to a respective set of target conditions using program pulses. At least a subset of the programming processes include identifying a program pulse associated with achieving a particular result for a respective programming process and performing one or more sensing operations at one or more alternative results for the non-volatile storage elements. Subsequent programming process are adjusted based on a first alternative result and the identification of the program pulse if the one or more sensing operations determined that greater than a predetermined number of non-volatile storage elements achieved the first alternative result. Subsequent programming process are adjusted based on the identification of the program pulse if the one or more sensing operations determined that less than a required number of non-volatile storage elements achieved any of the alternative results.

    Abstract translation: 编程过程中的每一个都使用编程脉冲来操作至少一个非易失性存储元件的子集到相应的目标条件集合。 编程过程的至少一个子集包括识别与实现相应编程处理的特定结果相关联的编程脉冲，并且以非易失性存储元件的一个或多个替代结果执行一个或多个感测操作。 如果一个或多个感测操作确定大于预定数量的非易失性存储元件实现了第一替代结果，则基于第一备选结果和编程脉冲的识别来调整后续编程处理。 如果一个或多个感测操作确定小于所需数量的非易失性存储元件实现任何替代结果，则基于编程脉冲的识别来调整后续编程处理。

    DETECTING THE COMPLETION OF PROGRAMMING FOR NON-VOLATILE STORAGE
    7.
    发明申请
    DETECTING THE COMPLETION OF PROGRAMMING FOR NON-VOLATILE STORAGE 有权
    检测完成非易失性存储的编程

    公开(公告)号：US20120033494A1

    公开(公告)日：2012-02-09

    申请号：US13237814

    申请日：2011-09-20

    Applicant: Gerrit Jan Hemink

    Inventor： Gerrit Jan Hemink

    IPC: G11C16/34 ,  G11C16/04

    CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/3454

    Abstract: A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target condition to store the appropriate data. Programming can be stopped when all non-volatile storage elements have reached their target level or when the number of non-volatile storage elements that have not reached their target level is less than a number or memory cells that can be corrected using an error correction process during a read operation (or other operation). The number of non-volatile storage elements that have not reached their target level can be estimated by counting the number of non-volatile storage elements that have not reached a condition that is different (e.g., lower) than the target level.

    Abstract translation: 对一组非易失性存储元件进行编程处理以便存储数据。 在编程过程中，执行一个或多个验证操作以确定非易失性存储元件是否已经达到其目标条件以存储适当的数据。 当所有非易失性存储元件已经达到其目标电平时或当尚未达到其目标电平的非易失性存储元件的数量小于可以使用纠错过程进行校正的数量或存储器单元时，可以停止编程 在读取操作期间（或其他操作）。 尚未达到其目标水平的非易失性存储元件的数量可以通过对尚未达到不同于目标水平的条件（例如，较低）的非易失性存储元件的数量进行计数来估计。

    SAW-SHAPED MULTI-PULSE PROGRAMMING FOR PROGRAM NOISE REDUCTION IN MEMORY
    8.
    发明申请
    SAW-SHAPED MULTI-PULSE PROGRAMMING FOR PROGRAM NOISE REDUCTION IN MEMORY 有权
    存储器中程序噪声减少的SAW形状多脉冲编程

    公开(公告)号：US20110249504A1

    公开(公告)日：2011-10-13

    申请号：US12757399

    申请日：2010-04-09

    Applicant: Yingda Dong ,  Yupin K. Fong ,  Gerrit Jan Hemink

    Inventor： Yingda Dong ,  Yupin K. Fong ,  Gerrit Jan Hemink

    IPC: G11C16/04 ,  G11C16/06

    CPC classification number: G11C16/04 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/10 ,  G11C2211/5621 ,  G11C2211/5622

    Abstract: In a memory system, a programming waveform reduces program noise by using sets of multiple adjacent sub-pulses which have a saw-tooth shape. In a set, an initial sub-pulse steps up from an initial level such as 0 V to a peak level, then steps down to an intermediate level, which is above the initial level. One or more subsequent sub-pulses of the set can step up from an intermediate level to a peak level, and then step back down to an intermediate level. A last sub-pulse of the set can step up from an intermediate level to a peak level, and then step back down to the initial level. A verify operation is performed after the set of sub-pulses. The number of sub-pulses per set can decrease in successive sets until a solitary pulse is applied toward the end of a programming operation.

    Abstract translation: 在存储器系统中，编程波形通过使用具有锯齿形状的多个相邻子脉冲的集合来减少编程噪声。 在一组中，初始子脉冲从初始电平（例如0V）升高到峰值电平，然后降至高于初始电平的中间电平。 该集合的一个或多个后续子脉冲可以从中间电平升高到峰值电平，然后降低到中间电平。 集合的最后一个子脉冲可以从中间电平升高到峰值电平，然后降低到初始电平。 在子脉冲组之后执行验证操作。 每组的子脉冲数可以在连续的集合中减小，直到在编程操作结束时施加孤立脉冲。

Patent Agency Ranking