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    INTELLIGENT CONTROL OF PROGRAM PULSE FOR NON-VOLATILE STORAGE
    1.
    发明申请
    INTELLIGENT CONTROL OF PROGRAM PULSE FOR NON-VOLATILE STORAGE 有权
    智能控制非挥发性存储的程序脉冲

    公开(公告)号：US20100046301A1

    公开(公告)日：2010-02-25

    申请号：US12607329

    申请日：2009-10-28

    Applicant: Yupin Fong ,  Jun Wan

    Inventor： Yupin Fong ,  Jun Wan

    IPC: G11C16/04

    CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

    Abstract: To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have a constant pulse width and increasing magnitudes until a maximum voltage is reached. At that point, the magnitude of the programming pulses stops increasing and the programming pulses are applied in a manner to provide varying time duration of the programming signal between verification operations. In one embodiment, for example, after the pulses reach the maximum magnitude the pulse widths are increased. In another embodiment, after the pulses reach the maximum magnitude multiple program pulses are applied between verification operations.

    Abstract translation: 为了对一组非易失性存储元件进行编程，将一组编程脉冲施加到非易失性存储元件的控制门（或其它终端）。 编程脉冲具有恒定的脉冲宽度和增加的幅度，直到达到最大电压。 在这一点上，编程脉冲的幅度停止增加，编程脉冲以一种方式施加，以便在验证操作之间提供编程信号的变化的持续时间。 在一个实施例中，例如，在脉冲达到最大幅度之后，脉冲宽度增加。 在另一个实施例中，在脉冲达到最大幅度之后，在验证操作之间施加多个编程脉冲。

    Reducing read disturb for non-volatile storage
    2.
    发明授权
    Reducing read disturb for non-volatile storage 有权

    公开(公告)号：US07447065B2

    公开(公告)日：2008-11-04

    申请号：US12021741

    申请日：2008-01-29

    Applicant: Yupin Fong ,  Jun Wan ,  Jeffrey Lutze

    Inventor： Yupin Fong ,  Jun Wan ,  Jeffrey Lutze

    IPC: G11C11/34

    CPC classification number: G11C16/3418 ,  G11C16/3427

    Abstract: A system is disclosed for reducing or removing a form of read disturb in a non-volatile storage device. One embodiment seeks to prevent read disturb by eliminating or minimizing boosting of the channel of the memory elements. For example, one implementation prevents or reduces boosting of the source side of the NAND string channel during a read process. Because the source side of the NAND string channel is not boosted, at least one form of read disturb is minimized or does not occur.

    Novel Multi-State Memory
    3.
    发明申请
    Novel Multi-State Memory 失效
    新型多态内存

    公开(公告)号：US20080043529A1

    公开(公告)日：2008-02-21

    申请号：US11868225

    申请日：2007-10-05

    Applicant: Daniel Guterman ,  Yupin Fong

    Inventor： Daniel Guterman ,  Yupin Fong

    IPC: G11C16/04

    CPC classification number: H01L27/115 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0425 ,  G11C16/0441 ,  G11C16/28 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/349 ,  G11C16/3495 ,  G11C27/005 ,  G11C29/00 ,  G11C29/76 ,  G11C2211/5634 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/7885

    Abstract: Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and process the data. In accordance with the teachings of this invention, the memory array is read with high fidelity, not to provide actual final digital data, but rather to provide raw data accurately reflecting the analog storage state, which information is sent to a memory controller for analysis and detection of the actual final digital data.

    Abstract translation: 通过灵活，自我一致和自适应的检测方式实现了最大化的多状态压缩和更多的记忆状态容忍度，涵盖了广泛的动态范围。 对于高密度多态编码，这种方法接近完全模拟处理，决定了模拟技术，包括A到D型转换，以重构和处理数据。 根据本发明的教导，以高保真度读取存储器阵列，而不是提供实际的最终数字数据，而是提供准确地反映模拟存储状态的原始数据，哪些信息被发送到存储器控制器用于分析和 检测实际的最终数字数据。

    Smart Verify For Multi-State Memories
    4.
    发明申请
    Smart Verify For Multi-State Memories 有权
    智能验证多状态记忆

    公开(公告)号：US20070234144A1

    公开(公告)日：2007-10-04

    申请号：US11759872

    申请日：2007-06-07

    Applicant: Geoffrey Gongwer ,  Daniel Guterman ,  Yupin Fong

    Inventor： Geoffrey Gongwer ,  Daniel Guterman ,  Yupin Fong

    IPC: G11C29/00

    CPC classification number: G11C11/5635 ,  G11C11/5628 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

    Abstract: A “smart verify” technique, whereby multi-state memories are programmed using a verify-results-based dynamic adjustment of the multi-states verify range for sequential-state-based verify implementations, is presented. This technique can increase multi-state write speed while maintaining reliable operation within sequentially verified, multi-state memory implementations by providing “intelligent” means to minimize the number of sequential verify operations for each program/verify/lockout step of the write sequence. At the beginning of a program/verify cycle sequence only the lowest state or states are checked during the verify phase. As lower states are reached, additional higher states are added to the verify sequence and lower states can be removed.

    Abstract translation: 提出了一种“智能验证”技术，其中使用基于验证结果的动态调整多状态验证范围对基于顺序状态的验证实现来编程多状态存储器。 这种技术可以通过提供“智能”手段来使顺序验证的多状态存储器实现中的可靠操作增加多状态写入速度，从而最小化写入序列的每个程序/验证/锁定步骤的顺序验证操作的数量。 在程序/验证周期序列的开始，在验证阶段只检查最低的状态或状态。 当达到较低的状态时，额外的更高的状态被添加到验证序列中，并且可以去除较低的状态。

    REDUCING FLOATING GATE TO FLOATING GATE COUPLING EFFECT
    6.
    发明申请
    REDUCING FLOATING GATE TO FLOATING GATE COUPLING EFFECT 有权
    降低浮动门到浮动联接效应

    公开(公告)号：US20070195602A1

    公开(公告)日：2007-08-23

    申请号：US11735265

    申请日：2007-04-13

    Applicant: Yupin Fong ,  Daniel Guterman

    Inventor： Yupin Fong ,  Daniel Guterman

    IPC: G11C16/04

    CPC classification number: G11C16/10 ,  G11C16/16

    Abstract: For a non-volatile memory system, compressing the erase threshold voltage distribution into the lowest threshold voltage state will decrease the valid data threshold voltage window. Decreasing the valid data threshold voltage window reduces the floating gate to floating gate coupling effect. The compression can be performed as part of the erase process or part of the programming operation.

    Abstract translation: 对于非易失性存储器系统，将擦除阈值电压分布压缩到最低阈值电压状态将降低有效数据阈值电压窗口。 降低有效的数据阈值电压窗口可以将浮栅减少到浮栅耦合效应。 压缩可以作为擦除过程的一部分或编程操作的一部分来执行。

    Charge packet metering for coarse/fine programming of non-volatile memory
    7.
    发明申请
    Charge packet metering for coarse/fine programming of non-volatile memory 有权
    充电数据包测量用于粗略/精细编程非易失性存储器

    公开(公告)号：US20060221700A1

    公开(公告)日：2006-10-05

    申请号：US11429769

    申请日：2006-05-08

    Applicant: Daniel Guterman ,  Nima Mokhlesi ,  Yupin Fong

    Inventor： Daniel Guterman ,  Nima Mokhlesi ,  Yupin Fong

    IPC: G11C16/04 ,  G11C11/34

    CPC classification number: G11C11/5628 ,  G11C16/10 ,  G11C2211/5621 ,  G11C2211/5624

    Abstract: A non-volatile memory device is programmed by first performing a coarse programming process and subsequently performing a fine programming process. The coarse/fine programming methodology is enhanced by using an efficient verification scheme that allows some non-volatile memory cells to be verified for the coarse programming process while other non-volatile memory cells are verified for the fine programming process. The fine programming process can be accomplished using current sinking, charge packet metering or other suitable means.

    Abstract translation: 通过首先执行粗略编程处理并随后执行精细编程处理来编程非易失性存储器件。 通过使用有效的验证方案来增强粗/精编程方法，该验证方案允许对粗略编程过程验证一些非易失性存储器单元，同时验证其它非易失性存储器单元用于精细编程过程。 精细的编程过程可以使用电流吸收，电荷分组测量或其他合适的方法来完成。

    Novel multi-state memory
    9.
    发明申请
    Novel multi-state memory 有权
    新型多状态存储器

    公开(公告)号：US20060129751A1

    公开(公告)日：2006-06-15

    申请号：US11330923

    申请日：2006-01-11

    Applicant: Daniel Guterman ,  Yupin Fong

    Inventor： Daniel Guterman ,  Yupin Fong

    IPC: G11C16/06 ,  G11C16/28 ,  G06F12/14

    CPC classification number: H01L27/115 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0425 ,  G11C16/0441 ,  G11C16/28 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/349 ,  G11C16/3495 ,  G11C27/005 ,  G11C29/00 ,  G11C29/76 ,  G11C2211/5634 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/7885

    Abstract: Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and- self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and process the data. In accordance with the teachings of this invention, the memory array is read with high fidelity, not to provide actual final digital data, but rather to provide raw data accurately reflecting the analog storage state, which information is sent to a memory controller for analysis and detection of the actual final digital data.

    Abstract translation: 通过灵活，自我一致和自适应的检测方式实现了最大化的多状态压缩和更大的内存状态容限，涵盖了广泛的动态范围。 对于高密度多态编码，这种方法接近完全模拟处理，决定了模拟技术，包括A到D型转换，以重构和处理数据。 根据本发明的教导，以高保真度读取存储器阵列，而不是提供实际的最终数字数据，而是提供准确地反映模拟存储状态的原始数据，哪些信息被发送到存储器控制器用于分析和 检测实际的最终数字数据。

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