公开(公告)号：US08473813B2

公开(公告)日：2013-06-25

申请号：US12984505

申请日：2011-01-04

Applicant: Carlos J. Gonzalez ,  Daniel C. Guterman

Inventor： Carlos J. Gonzalez ,  Daniel C. Guterman

IPC: G11C29/00

CPC classification number: G11C29/50 ,  G11C16/04 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3422 ,  G11C29/028 ,  G11C29/42 ,  G11C29/46 ,  G11C29/50004 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: A memory using techniques to extract the data content of its storage elements, when the distribution of stored states is degraded, is presented. If the distribution of stored states has degraded, secondary evaluations of the memory cells are performed using modified read conditions. Based upon the results of these supplemental evaluations, the memory device determines the read conditions at which to best decide the data stored.

Abstract translation: 提出了当存储状态的分布降级时使用技术来提取其存储元件的数据内容的存储器。 如果存储状态的分布已经降级，则使用修改的读取条件来执行存储器单元的二次评估。 基于这些补充评估的结果，存储器件确定最佳地确定存储的数据的读取条件。

公开(公告)号：US07796444B2

公开(公告)日：2010-09-14

申请号：US11936086

申请日：2007-11-07

Applicant: Daniel C. Guterman

Inventor： Daniel C. Guterman

IPC: G11C7/10

CPC classification number: G11C16/0483 ,  G11C16/10

Abstract: One embodiment of the present invention includes applying a first value to a bit line, boosting word lines associated with the bit line and a common selection line to create a first condition based on the first value, and cutting off a boundary non-volatile storage element associated with the common selection line to maintain the first condition for a particular non-volatile storage element associated with the bit line and common selection line. A second value is applied to the bit line and at least a subset of the word lines are boosted to create a second condition for a different non-volatile storage element associated with the bit line and common selection line. The second condition is based on the second value. The first condition and the second condition overlap in time. Both non-volatile storage elements are programmed concurrently, based on their associated conditions.

公开(公告)号：US07739472B2

公开(公告)日：2010-06-15

申请号：US11286100

申请日：2005-11-22

Applicant: Daniel C. Guterman ,  Yoram Cedar ,  Charles Schroter ,  Milton Lourenco Barrocas ,  Carlos Gonzalez ,  Kevin M. Conley

Inventor： Daniel C. Guterman ,  Yoram Cedar ,  Charles Schroter ,  Milton Lourenco Barrocas ,  Carlos Gonzalez ,  Kevin M. Conley

IPC: G06F12/00

CPC classification number: G06F3/0664 ,  G06F3/0607 ,  G06F3/0661 ,  G06F3/0679 ,  G06F11/1048 ,  G06F13/385

Abstract: A non-volatile memory device is provided with a controller and includes method that controls memory operations and to emulate the memory and communication characteristics of a legacy memory device. In this way, the memory device is compatible with a host that was originally designed to operate the legacy memory device. In particular, the controller performs the emulation to the host taking into account differences such as multibit memory, error correction requirement, memory support of overwrites, and erasable block sizes.

Abstract translation: 非易失性存储器件具有控制器，并且包括控制存储器操作并模拟传统存储器件的存储器和通信特性的方法。 以这种方式，存储器设备与最初设计用于操作传统存储设备的主机兼容。 特别地，控制器考虑到诸如多位存储器，错误校正要求，覆盖的存储器支持以及可擦除块大小之类的差异，对主机执行仿真。

公开(公告)号：US20090296469A1

公开(公告)日：2009-12-03

申请号：US12538773

申请日：2009-08-10

Applicant: Daniel C. Guterman

Inventor： Daniel C. Guterman

IPC: G11C16/04 ,  G11C16/06

CPC classification number: G11C16/3418 ,  G11C16/3427

Abstract: A set of storage elements is programmed beginning with a word line WLn adjacent a select gate line for the set. After programming the first word line, the next word line WLn+1 adjacent to the first word line is skipped and the next word line WLn+2 adjacent to WLn+1 is programmed. WLn+1 is then programmed. Programming continues according to the sequence {WLn+4, WLn+3, WLn+6, WLn+5, . . . } until all but the last word line for the set have been programmed. The last word line is then programmed. By programming in this manner, some of the word lines of the set (WLn+1, WLn+3, etc.) have no subsequently programmed neighboring word lines. The memory cells of these word lines will not experience any floating gate to floating gate coupling threshold voltage shift impact due to subsequently programmed neighboring memory cells. The word lines having no subsequently programmed neighbors are read without using offsets or compensations based on neighboring memory cells. The other word lines are read using compensations based on data states within both subsequently programmed neighboring word lines.

Abstract translation: 一组存储元件从与集合的选择栅极线相邻的字线WLn开始被编程。 在对第一字线进行编程之后，跳过与第一字线相邻的下一个字线WLn + 1，并对与WLn + 1相邻的下一个字线WLn + 2进行编程。 然后编程WLn + 1。 根据序列{WLn + 4，WLn + 3，WLn + 6，WLn + 5，...， 。 。 }直到所有集合的最后一个字线都被编程为止。 然后编程最后一个字线。 通过以这种方式进行编程，组（WLn + 1，WLn + 3等）的一些字线没有随后编程的相邻字线。 这些字线的存储单元将不会经历由于随后编程的相邻存储单元而产生的任何漂浮栅极与浮栅耦合阈值电压偏移的影响。 在不使用基于相邻存储器单元的偏移或补偿的情况下读取没有随后编程的邻居的字线。 使用基于随后编程的相邻字线内的数据状态的补偿来读取其他字线。

公开(公告)号：US07616484B2

公开(公告)日：2009-11-10

申请号：US10974366

申请日：2004-10-26

Applicant: Daniel L. Auclair ,  Jeffrey Craig ,  John S. Mangan ,  Robert D. Norman ,  Daniel C. Guterman ,  Sanjay Mehrotra

Inventor： Daniel L. Auclair ,  Jeffrey Craig ,  John S. Mangan ,  Robert D. Norman ,  Daniel C. Guterman ,  Sanjay Mehrotra

IPC: G11C16/06 ,  G11C16/04 ,  G11C29/00 ,  G08C25/00

CPC classification number: G11C29/028 ,  G06F11/1068 ,  G06F11/1072 ,  G06F2201/81 ,  G11C16/04 ,  G11C16/10 ,  G11C16/3431 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/52 ,  G11C2029/5004 ,  G11C2029/5006

Abstract: Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.

Abstract translation: 正常使用固态存储器（如EEP​​ROM或闪存EEPROM）时会发生软错误。 存储器单元的编程阈值电压从原来的预期电平漂移导致软错误。 在正常读取期间，最初不容易检测到该误差，直到累积漂移变得如此严重以致其发展为硬错误。 数据可能会丢失，如果这些硬错误足够的可以在存储器中发出可用的纠错码。 一种存储器件及其技术能够在整个使用存储器件的过程中检测这些漂移并且将每个存储器单元的阈值电压基本上保持在其预期的水平，从而抵抗将软错误发展成硬错误。

公开(公告)号：US07579247B2

公开(公告)日：2009-08-25

申请号：US12020296

申请日：2008-01-25

Applicant: Eliyahou Harari ,  George Samachisa ,  Jack H. Yuan ,  Daniel C. Guterman

Inventor： Eliyahou Harari ,  George Samachisa ,  Jack H. Yuan ,  Daniel C. Guterman

IPC: H01L21/8239

CPC classification number: H01L27/11568 ,  B82Y10/00 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/0491 ,  G11C2216/06 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/4234 ,  H01L29/7923 ,  Y10S438/947

Abstract: Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions in a cell that also includes a select transistor positioned between them. In another form, NAND arrays of strings of memory cells store charge in regions of a dielectric layer sandwiched between word lines and the semiconductor substrate.

Abstract translation: 非易失性存储单元存储对应于存储在存储单元的沟道区上夹在控制栅极和半导体衬底表面之间的介电材料存储元件中的数据的电荷水平。 通过存储在电介质材料的公共区域中的多于两个的电荷中的一个来提供两个以上的记忆状态。 每个单元中可以包括多于一个这样的共同区域。 在一种形式中，在单元中邻近的源和漏扩散设置了两个这样的区域，该单元还包括位于它们之间的选择晶体管。 在另一种形式中，存储单元串的NAND阵列在夹在字线和半导体衬底之间的电介质层的区域中存储电荷。

公开(公告)号：US07573747B2

公开(公告)日：2009-08-11

申请号：US11933348

申请日：2007-10-31

Applicant: Daniel C Guterman

Inventor： Daniel C Guterman

IPC: G11C11/34

CPC classification number: G11C16/3418 ,  G11C16/3427

Abstract: A set of storage elements is programmed beginning with a word line WLn adjacent a select gate line for the set. After programming the first word line, the next word line WLn+1 adjacent to the first word line is skipped and the next word line WLn+2 adjacent to WLn+1 is programmed. WLn+1 is then programmed. Programming continues according to the sequence {WLn+4, WLn+3, WLn+6, WLn+5, . . . } until all but the last word line for the set have been programmed. The last word line is then programmed. By programming in this manner, some of the word lines of the set (WLn+1, WLn+3, etc.) have no subsequently programmed neighboring word lines. The memory cells of these word lines will not experience any floating gate to floating gate coupling threshold voltage shift impact due to subsequently programmed neighboring memory cells. The word lines having no subsequently programmed neighbors are read without using offsets or compensations based on neighboring memory cells. The other word lines are read using compensations based on data states within both subsequently programmed neighboring word lines.

Abstract translation: 一组存储元件从与集合的选择栅极线相邻的字线WLn开始被编程。 在对第一字线进行编程之后，跳过与第一字线相邻的下一个字线WLn + 1，并对与WLn + 1相邻的下一个字线WLn + 2进行编程。 然后编程WLn + 1。 根据序列{WLn + 4，WLn + 3，WLn + 6，WLn + 5，...， 。 。 }直到所有集合的最后一个字线都被编程为止。 然后编程最后一个字线。 通过以这种方式进行编程，组（WLn + 1，WLn + 3等）的一些字线没有随后编程的相邻字线。 这些字线的存储单元将不会经历由于随后编程的相邻存储单元而产生的任何漂浮栅极与浮栅耦合阈值电压偏移的影响。 在不使用基于相邻存储器单元的偏移或补偿的情况下读取没有随后编程的邻居的字线。 使用基于随后编程的相邻字线内的数据状态的补偿来读取其他字线。

公开(公告)号：US07479677B2

公开(公告)日：2009-01-20

申请号：US12020266

申请日：2008-01-25

Applicant: Eliyahou Harari ,  George Samachisa ,  Jack H. Yuan ,  Daniel C. Guterman

Inventor： Eliyahou Harari ,  George Samachisa ,  Jack H. Yuan ,  Daniel C. Guterman

IPC: H01L29/792

CPC classification number: H01L27/11568 ,  B82Y10/00 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/0491 ,  G11C2216/06 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/4234 ,  H01L29/7923 ,  Y10S438/947

Abstract: Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions in a cell that also includes a select transistor positioned between them. In another form, NAND arrays of strings of memory cells store charge in regions of a dielectric layer sandwiched between word lines and the semiconductor substrate.

公开(公告)号：US07447075B2

公开(公告)日：2008-11-04

申请号：US11429770

申请日：2006-05-08

Applicant: Daniel C. Guterman ,  Nima Mokhlesi ,  Yupin Fong

Inventor： Daniel C. Guterman ,  Nima Mokhlesi ,  Yupin Fong

IPC: G11C11/34

CPC classification number: G11C11/5628 ,  G11C16/10 ,  G11C2211/5621 ,  G11C2211/5624

Abstract: A non-volatile memory device is programmed by first performing a coarse programming process and subsequently performing a fine programming process. The coarse/fine programming methodology is enhanced by using an efficient verification scheme that allows some non-volatile memory cells to be verified for the coarse programming process while other non-volatile memory cells are verified for the fine programming process. The fine programming process can be accomplished using current sinking, charge packet metering or other suitable means.

Abstract translation: 通过首先执行粗略编程处理并随后执行精细编程处理来编程非易失性存储器件。 通过使用有效的验证方案来增强粗/精编程方法，该验证方案允许对粗略编程过程验证一些非易失性存储器单元，同时验证其它非易失性存储器单元用于精细编程过程。 精细的编程过程可以使用电流吸收，电荷分组测量或其他合适的方法来完成。

公开(公告)号：US20080212374A1

公开(公告)日：2008-09-04

申请号：US12110489

申请日：2008-04-28

Applicant: Daniel C. Guterman ,  Yupin Kawing Fong

Inventor： Daniel C. Guterman ,  Yupin Kawing Fong

IPC: G11C16/06

CPC classification number: H01L27/115 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0425 ,  G11C16/0441 ,  G11C16/28 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/349 ,  G11C16/3495 ,  G11C27/005 ,  G11C29/00 ,  G11C29/76 ,  G11C2211/5634 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/7885

Abstract: Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and process the data. In accordance with the teachings of this invention, the memory array is read with high fidelity, not to provide actual final digital data, but rather to provide raw data accurately reflecting the analog storage state, which information is sent to a memory controller for analysis and detection of the actual final digital data.