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    Tracking cells for a memory system
    1.
    发明授权
    Tracking cells for a memory system 有权
    跟踪单元格的内存系统

    公开(公告)号：US07916552B2

    公开(公告)日：2011-03-29

    申请号：US12763569

    申请日：2010-04-20

    Applicant: Daniel C. Guterman ,  Stephen J. Gross ,  Shazad Khalid ,  Geoffrey S. Gongwer

    Inventor： Daniel C. Guterman ,  Stephen J. Gross ,  Shazad Khalid ,  Geoffrey S. Gongwer

    IPC: G11C16/04

    CPC classification number: G11C16/26 ,  G11C11/5621 ,  G11C16/349

    Abstract: Tracking cells are used in a memory system to improve the read process. The tracking cells can provide an indication of the quality of the data and can be used as part of a data recovery operation if there is an error. The tracking cells provide a means to adjust the read parameters to optimum levels in order to reflect the current conditions of the memory system. Additionally, some memory systems that use multi-state memory cells will apply rotation data schemes to minimize wear. The rotation scheme can be encoded in the tracking cells based on the states of multiple tracking cells, which is decoded upon reading.

    Abstract translation: 在存储器系统中使用跟踪单元来改善读取过程。 跟踪单元可以提供数据质量的指示，如果存在错误，可以将其用作数据恢复操作的一部分。 跟踪单元提供了将读取参数调整到最佳水平以便反映存储器系统的当前状况的手段。 另外，使用多状态存储器单元的一些存储器系统将应用旋转数据方案以最小化磨损。 可以基于多个跟踪单元的状态在跟踪单元中编码旋转方案，该单元在读取时被解码。

    Reducing the effects of noise in non-volatile memories through multiple reads
    2.
    发明授权
    Reducing the effects of noise in non-volatile memories through multiple reads 有权
    通过多次读取降低非易失性存储器中噪声的影响

    公开(公告)号：US07848149B2

    公开(公告)日：2010-12-07

    申请号：US11674000

    申请日：2007-02-12

    Applicant: Carlos J. Gonzalez ,  Daniel C. Guterman

    Inventor： Carlos J. Gonzalez ,  Daniel C. Guterman

    IPC: G11C11/34

    CPC classification number: G11C7/106 ,  G11C7/1006 ,  G11C7/1051 ,  G11C16/12 ,  G11C16/26 ,  G11C16/28 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2013/0057

    Abstract: Storage elements are read multiple times and the results are accumulated and averaged for each storage element to reduce the effects of noise or other transients in the storage elements and associated circuits that may adversely affect the quality of the read. Several techniques may be employed, including: A full read and transfer of the data from the storage device to the controller device for each iteration, with averaging performed by the controller; a full read of the data for each iteration, with the averaging performed by the storage device, and no transfer to the controller until the final results are obtained; one full read followed by a number of faster re-reads exploiting the already established state information to avoid a full read, followed by an intelligent algorithm to guide the state at which the storage element is sensed. These techniques may be used as the normal mode of operation, or invoked upon exception condition, depending on the system characteristics. A similar form of signal averaging may be employed during the verify phase of programming. An embodiment of this technique would use a peak-detection scheme. In this scenario, several verify checks are performed at the state prior to deciding if the storage element has reached the target state. If some predetermined portion of the verifies fail, the storage element receives additional programming. These techniques allow the system to store more states per storage element in the presence of various sources of noise.

    Abstract translation: 存储元件被读取多次，并且对于每个存储元件累积和平均结果，以减少可能不利地影响读取质量的存储元件和相关电路中的噪声或其他瞬变的影响。 可以采用几种技术，其中包括：由控制器对平均数据进行每次迭代从存储设备到控制器设备的完整读取和传输; 对每次迭代的数据进行完全读取，并由存储设备进行平均，并且在获得最终结果之前不转移到控制器; 一次完全读取，然后利用已建立的状态信息进行多次更快的重新读取，以避免完全读取，随后是引导存储元件被感测的状态的智能算法。 这些技术可以用作正常操作模式，或者根据异常情况被调用，这取决于系统特性。 可以在编程的验证阶段期间采用类似形式的信号平均。 该技术的实施例将使用峰值检测方案。 在这种情况下，在决定存储元件是否达到目标状态之前，先在状态下执行多个验证检查。 如果验证的一些预定部分失败，则存储元件接收另外的编程。 这些技术允许系统在存在各种噪声源的情况下存储每个存储元件的更多状态。

    TRACKING CELLS FOR A MEMORY SYSTEM
    3.
    发明申请
    TRACKING CELLS FOR A MEMORY SYSTEM 有权
    跟踪记忆系统的细胞

    公开(公告)号：US20100202199A1

    公开(公告)日：2010-08-12

    申请号：US12763569

    申请日：2010-04-20

    Applicant: Daniel C. Guterman ,  Stephen J. Gross ,  Shazad Khalid ,  Geoffrey S. Gongwer

    Inventor： Daniel C. Guterman ,  Stephen J. Gross ,  Shazad Khalid ,  Geoffrey S. Gongwer

    IPC: G11C16/02 ,  G11C16/04

    CPC classification number: G11C16/26 ,  G11C11/5621 ,  G11C16/349

    Abstract: Tracking cells are used in a memory system to improve the read process. The tracking cells can provide an indication of the quality of the data and can be used as part of a data recovery operation if there is an error. The tracking cells provide a means to adjust the read parameters to optimum levels in order to reflect the current conditions of the memory system. Additionally, some memory systems that use multi-state memory cells will apply rotation data schemes to minimize wear. The rotation scheme can be encoded in the tracking cells based on the states of multiple tracking cells, which is decoded upon reading.

    Abstract translation: 在存储器系统中使用跟踪单元来改善读取过程。 跟踪单元可以提供数据质量的指示，如果存在错误，可以将其用作数据恢复操作的一部分。 跟踪单元提供了将读取参数调整到最佳水平以便反映存储器系统的当前状况的手段。 另外，使用多状态存储器单元的一些存储器系统将应用旋转数据方案以最小化磨损。 可以基于多个跟踪单元的状态在跟踪单元中编码旋转方案，该单元在读取时被解码。

    Removable Mother/Daughter Peripheral Card
    4.
    发明申请
    Removable Mother/Daughter Peripheral Card 审中-公开
    可拆卸的母亲/女儿外围卡

    公开(公告)号：US20100169559A1

    公开(公告)日：2010-07-01

    申请号：US12723491

    申请日：2010-03-12

    Applicant: Eliyahou Harari ,  Daniel C. Guterman ,  Robert F. Wallace

    Inventor： Eliyahou Harari ,  Daniel C. Guterman ,  Robert F. Wallace

    IPC: G06F13/00 ,  G06F12/02

    CPC classification number: G06F13/4068 ,  G06K19/07741 ,  H05K5/0265 ,  H05K5/0282

    Abstract: A peripheral card having a Personal Computer (“PC”) card form factor and removably coupled externally to a host system is further partitioned into a mother card portion and a daughter card portion. The daughter card is removably coupled to the mother card. In the preferred embodiment, a low cost flash “floppy” is accomplished with the daughter card containing only flash EEPROM chips and being controlled by a memory controller residing on the mother card. Other aspects of the invention includes a comprehensive controller on the mother card able to control a predefined set of peripherals on daughter cards connectable to the mother card; relocation of some host resident hardware to the mother card to allow for a minimal host system; a mother card that can accommodate multiple daughter cards; daughter cards that also operates directly with hosts having embedded controllers; daughter cards carrying encoded data and information for decoding it; and daughter cards with security features.

    Abstract translation: 具有个人计算机（“PC”）卡形状因子并且可拆卸地耦合到主机系统外部的外围卡进一步被划分为母卡部分和子卡部分。 子卡可拆卸地耦合到母卡。 在优选实施例中，低成本闪存“软盘”是通过仅包含快闪EEPROM芯片的子卡并由驻留在母卡上的存储器控​​制器来控制的。 本发明的其它方面包括：母卡上的综合控制器，其能够控制可连接到母卡的子卡上的预定义的一组外围设备; 将一些主机驻地硬件重定位到母卡以允许最小的主机系统; 可容纳多张子卡的母卡; 子卡也直接与具有嵌入式控制器的主机操作; 携带编码数据的子卡和用于解码的信息; 和具有安全功能的子卡。

    System and Method for Programming Cells in Non-Volatile Integrated Memory Devices
    5.
    发明申请
    System and Method for Programming Cells in Non-Volatile Integrated Memory Devices 有权
    用于在非易失性集成存储器件中编程单元的系统和方法

    公开(公告)号：US20100039859A1

    公开(公告)日：2010-02-18

    申请号：US12604904

    申请日：2009-10-23

    Applicant: Nima Mokhlesi ,  Daniel C. Guterman

    Inventor： Nima Mokhlesi ,  Daniel C. Guterman

    IPC: G11C16/04

    CPC classification number: G11C16/12 ,  G11C11/5628 ,  G11C11/5671 ,  G11C16/3459 ,  G11C16/3468 ,  G11C16/3481 ,  G11C2211/5621

    Abstract: A system and method for quickly and efficiently programming hard-to-program storage elements in non-volatile integrated memory devices is presented. A number of storage elements are simultaneously subjected to a programming process with the current flowing through the storage elements limited to a first level. As a portion of these storage elements reach a prescribed state, they are removed from the set of cells being programmed and the current limit on the elements that continue to be programmed is raised. The current level in these hard-to-program cells can be raised to a second, higher limit or unregulated. According to another aspect, during a program operation the current limit allowed for a cell depends upon the target state to which it is to be programmed.

    Abstract translation: 提出了一种用于在非易失性集成存储器件中快速高效地编程难编程存储元件的系统和方法。 多个存储元件同时进行编程处理，其中流过存储元件的电流限于第一级。 随着这些存储元件的一部分达到规定的状态，它们被从被编程的单元组移除，并且提高了继续编程的元件上的电流限制。 这些难以编程的单元格中的当前级别可以提高到第二个，更高的限制或不受管制。 根据另一方面，在程序操作期间，允许单元的电流限制取决于要被编程的目标状态。

    Behavior based programming of non-volatile memory
    6.
    发明授权
    Behavior based programming of non-volatile memory 有权
    非易失性存储器的基于行为的编程

    公开(公告)号：US07633807B2

    公开(公告)日：2009-12-15

    申请号：US11624052

    申请日：2007-01-17

    Applicant: Jian Chen ,  Jeffrey W. Lutze ,  Yan Li ,  Daniel C. Guterman ,  Tomoharu Tanaka

    Inventor： Jian Chen ,  Jeffrey W. Lutze ,  Yan Li ,  Daniel C. Guterman ,  Tomoharu Tanaka

    IPC: G11C16/04

    CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3454 ,  G11C16/3459

    Abstract: The process for programming a set of memory cells is improved by adapting the programming process based on behavior of the memory cells. For example, a set of program pulses is applied to the word line for a set of flash memory cells. A determination is made as to which memory cells are easier to program and which memory cells are harder to program. Bit line voltages (or other parameters) can be adjusted based on the determination of which memory cells are easier to program and which memory cells are harder to program. The programming process will then continue with the adjusted bit line voltages (or other parameters).

    Abstract translation: 通过基于存储器单元的行为调整编程过程来改进用于对一组存储器单元进行编程的过程。 例如，一组编程脉冲被施加到一组闪存单元的字线。 确定哪些存储器单元更容易编程，哪些存储器单元难以编程。 可以基于确定哪些存储器单元更容易编程以及哪些存储器单元难以编程来调整位线电压（或其他参数）。 然后，编程过程将继续调整的位线电压（或其他参数）。

    EEPROM with split gate source side injection
    9.
    发明授权
    EEPROM with split gate source side injection 失效
    带分流栅源的EEPROM注入

    公开(公告)号：US07449746B2

    公开(公告)日：2008-11-11

    申请号：US11278778

    申请日：2006-04-05

    Applicant: Daniel C. Guterman ,  Gheorghe Samachisa ,  Yupin Kawing Fong ,  Eliyahou Harari

    Inventor： Daniel C. Guterman ,  Gheorghe Samachisa ,  Yupin Kawing Fong ,  Eliyahou Harari

    IPC: H01L29/94

    CPC classification number: H01L27/11521 ,  G11C16/0425 ,  G11C16/0458 ,  G11C16/0491 ,  H01L27/115 ,  H01L29/7881

    Abstract: Novel memory cells utilize source-side injection, allowing very small programming currents. If desired, to-be-programmed cells are programmed simultaneously while not requiring an unacceptably large programming current for any given programming operation. In one embodiment, memory arrays are organized in sectors with each sector being formed of a single column or a group of columns having their control gates connected in common. In one embodiment, a high speed shift register is used in place of a row decoder to serially shift in data for the word lines, with all data for each word line of a sector being contained in the shift register on completion of its serial loading. In one embodiment, speed is improved by utilizing a parallel loaded buffer register which receives parallel data from the high speed shift register and holds that data during the write operation, allowing the shift register to receive serial loaded data during the write operation for use in a subsequent write operation. In one embodiment, a verification is performed in parallel on all to-be-programmed cells in a column and the bit line current monitored. If all of the to-be-programmed cells have been properly programmed, the bit line current will be substantially zero. If bit line current is detected, another write operation is performed on all cells of the sector, and another verify operation is performed. This write/verify procedure is repeated until verification is successful, as detected or substantially zero, bit line current.

    Abstract translation: 新型存储单元利用源侧注入，允许非常小的编程电流。 如果需要，对于任何给定的编程操作，被编程的单元被同时编程，而不需要不可接受的大的编程电流。 在一个实施例中，存储器阵列被组织在扇区中，其中每个扇区由单个列或一组具有共同连接的控制门的列组成。 在一个实施例中，代替行解码器来使用高速移位寄存器来对字线的数据进行串行移位，在其串行加载完成时扇区的每个字线的所有数据都包含在移位寄存器中。 在一个实施例中，通过利用并行加载的缓冲寄存器来提高速度，所述缓冲寄存器从高速移位寄存器接收并行数据，并且在写入操作期间保持该数据，从而允许移位寄存器在写操作期间接收串行加载的数据，以用于 后续写操作。 在一个实施例中，在列中的所有要编程的单元并行地执行验证，并监视位线电流。 如果所有待编程的单元都已被正确编程，则位线电流将基本为零。 如果检测到位线电流，则对扇区的所有单元执行另一写操作，并且执行另一验证操作。 重复此写/验证过程，直到验证成功，如检测到或基本为零，位线电流。

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