公开(公告)号：US20230360903A1

公开(公告)日：2023-11-09

申请号：US17737340

申请日：2022-05-05

Applicant: Applied Materials, Inc.

Inventor： Supriya Ghosh ,  Susmit Singha Roy ,  Abhijit Basu Mallick

IPC: H01L21/02

CPC classification number: H01L21/02123 ,  H01L21/02211 ,  H01L21/02345 ,  H01L21/0234

Abstract: Exemplary methods of semiconductor processing may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The substrate may define one or more features along the substrate. The methods may include depositing a silicon-containing material on the substrate. The silicon-containing material may extend within the one or more features along the substrate. The methods may include providing an oxygen-containing precursor. The methods may include annealing the silicon-containing material with the oxygen-containing precursor. The annealing may cause the silicon-containing material to expand within the one or more features. The methods may include repeating one or more of the operations to iteratively fill the one or more features on the substrate.

公开(公告)号：US11735414B2

公开(公告)日：2023-08-22

申请号：US17352330

申请日：2021-06-20

Applicant: ASM IP Holding B.V.

Inventor： Toshiya Suzuki

IPC: H01L21/02 ,  H01L21/311 ,  H01L21/3105 ,  C23C16/40 ,  H10B69/00 ,  C23C16/56

CPC classification number: H01L21/0234 ,  C23C16/402 ,  H01L21/0228 ,  H01L21/02164 ,  H01L21/02219 ,  H01L21/02274 ,  H01L21/3105 ,  H01L21/31111 ,  H10B69/00 ,  C23C16/401 ,  C23C16/56

Abstract: A method of post-deposition treatment for silicon oxide film includes: providing in a reaction space a substrate having a recess pattern on which a silicon oxide film is deposited; supplying a reforming gas for reforming the silicon oxide film to the reaction space in the absence of a film-forming precursor, said reforming gas being composed primarily of He and/or H2; and irradiating the reforming gas with microwaves in the reaction space having a pressure of 200 Pa or less to generate a direct microwave plasma to which the substrate is exposed, thereby reforming the silicon oxide film.

公开(公告)号：US11699585B2

公开(公告)日：2023-07-11

申请号：US17075967

申请日：2020-10-21

Applicant: Applied Materials, Inc.

Inventor： Jui-Yuan Hsu ,  Pramit Manna ,  Bhaskar Kumar ,  Karthik Janakiraman

IPC: H01L21/02 ,  H01L21/033

CPC classification number: H01L21/0234 ,  H01L21/02115 ,  H01L21/02274 ,  H01L21/0332

Abstract: Embodiments of the present disclosure generally relate to methods of forming hardmasks. Embodiments described herein enable, e.g., formation of carbon-containing hardmasks having reduced film stress. In an embodiment, a method of processing a substrate is provided. The method includes positioning a substrate in a processing volume of a processing chamber and depositing a diamond-like carbon (DLC) layer on the substrate. After depositing the DLC layer, the film stress is reduced by performing a plasma treatment, wherein the plasma treatment comprises applying a radio frequency (RF) bias power of about 100 W to about 10,000 W.

公开(公告)号：US20230207311A1

公开(公告)日：2023-06-29

申请号：US18068805

申请日：2022-12-20

Applicant: COMMISSARIAT A L`ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Pierre BRIANCEAU ,  Nicolas POSSEME

IPC: H01L21/02 ,  H01L21/762

CPC classification number: H01L21/0234 ,  H01L21/762 ,  H01L21/02123 ,  H01L21/02208 ,  H01L21/02274

Abstract: A method for activating an exposed layer of a structure including a provision of a structure including an exposed layer, a deposition of a layer based on a material of formula SiaYbXc, with X chosen from among fluorine F and chlorine Cl, and Y chosen from among oxygen O and nitrogen N, a, b and c being non-zero positive integers, a treatment of the layer SiaYbXc by an activation plasma based on at least one from among oxygen and nitrogen, the parameters of the deposition of the layer SiaYbXc being chosen so as to obtain a sufficiently low material density such that the layer SiaYbXc is at least partially consumed by the activation plasma.

公开(公告)号：US11688606B2

公开(公告)日：2023-06-27

申请号：US17648159

申请日：2022-01-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shao-Jyun Wu ,  Sheng-Liang Pan ,  Huan-Just Lin

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  G03F7/09 ,  H01L29/66 ,  H01L21/027 ,  H01L21/3213 ,  H01L27/092 ,  H01L29/08 ,  H01L29/49 ,  G03F7/16 ,  G03F7/20 ,  G03F7/26 ,  H01L21/32 ,  H01L21/30 ,  H01L21/3205 ,  H01L21/324

CPC classification number: H01L21/28185 ,  G03F7/091 ,  G03F7/16 ,  G03F7/20 ,  G03F7/26 ,  H01L21/0234 ,  H01L21/0276 ,  H01L21/02252 ,  H01L21/28088 ,  H01L21/28158 ,  H01L21/28176 ,  H01L21/28211 ,  H01L21/30 ,  H01L21/32 ,  H01L21/324 ,  H01L21/3205 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/4966 ,  H01L29/66545

Abstract: A method includes forming a first high-k dielectric layer over a first semiconductor region, forming a second high-k dielectric layer over a second semiconductor region, forming a first metal layer comprising a first portion over the first high-k dielectric layer and a second portion over the second high-k dielectric layer, forming an etching mask over the second portion of the first metal layer, and etching the first portion of the first metal layer. The etching mask protects the second portion of the first metal layer. The etching mask is ashed using meta stable plasma. A second metal layer is then formed over the first high-k dielectric layer.

公开(公告)号：US20230197441A1

公开(公告)日：2023-06-22

申请号：US17992238

申请日：2022-11-22

Applicant: SPTS Technologies Limited

Inventor： Roland Mumford ,  Christopher Jonathan W. Bolton

IPC: H01L21/02 ,  H01L21/3065

CPC classification number: H01L21/02274 ,  H01L21/0234 ,  H01L21/3065 ,  H01L21/67063

Abstract: Surface roughness on a non-planar surface of a silicon substrate with upstanding and/or recessed features can be reduced. A first sequence of plasma processing steps and a second sequence of plasma processing steps can be performed on the silicon substrate to reduce the surface roughness of the upstanding and/or recessed features while retaining these features. The first sequence of plasma processing steps includes i) a plasma deposition step using oxygen and at least one fluorocarbon gas followed by ii) a plasma etch step using oxygen, at least one fluorocarbon etchant gas, and SF6. The second sequence of plasma processing steps includes i) an isotropic plasma etch step using oxygen and at least one fluorine containing etchant gas followed by ii) a plasma etch step using at least one fluorine containing or chlorine containing etchant gas.

公开(公告)号：US20230154745A1

公开(公告)日：2023-05-18

申请号：US18155507

申请日：2023-01-17

Applicant: Tokyo Electron Limited

Inventor： Jianping Zhao ,  Peter Lowell George Ventzek ,  Toshihiko Iwao

IPC: H01L21/02 ,  C23C16/34

CPC classification number: H01L21/02247 ,  H01L21/0234 ,  C23C16/345 ,  H01L21/0217

Abstract: A method of nitridation includes cyclically performing the following steps in situ within a processing chamber at a temperature less than about 400° C.: directing an energy flux to a localized region of an unreactive surface of a substrate to convert the localized region of the unreactive surface to a localized reactive region: and selectively nitridating the localized reactive region using a nitrogen-based gas to convert the localized reactive region to a nitride layer.

公开(公告)号：US20190203332A1

公开(公告)日：2019-07-04

申请号：US16292925

申请日：2019-03-05

Applicant: Applied Materials, Inc.

Inventor： Christopher S. OLSEN

IPC: C23C8/36 ,  H01L21/768 ,  H01L21/3115 ,  H01L21/02 ,  C23C8/02 ,  H01L27/115

CPC classification number: C23C8/36 ,  C23C8/02 ,  H01L21/02323 ,  H01L21/0234 ,  H01L21/3115 ,  H01L21/76814 ,  H01L21/76816 ,  H01L21/76826 ,  H01L21/76831 ,  H01L27/115

Abstract: Embodiments disclosed herein generally related to system for forming a semiconductor structure. The processing chamber includes a chamber body, a substrate support device, a quartz envelope, one or more heating devices, a gas injection assembly, and a pump device. The chamber body defines an interior volume. The substrate support device is configured to support one or more substrates during processing. The quartz envelope is disposed in the processing chamber. The quartz envelope is configured to house the substrate support device. The heating devices are disposed about the quartz envelope. The gas injection assembly is coupled to the processing chamber. The gas injection assembly is configured to provide an NH3 gas to the interior volume of the processing chamber. The pump device is coupled to the processing chamber. The pump device is configured to maintain the processing chamber at a pressure of at least 10 atm.

公开(公告)号：US20190096690A1

公开(公告)日：2019-03-28

申请号：US15717076

申请日：2017-09-27

Applicant: Lam Research Corporation

Inventor： Andreas FISCHER ,  Nerissa DRAEGER

IPC: H01L21/311 ,  H01L21/02 ,  H01L21/67

CPC classification number: H01L21/31105 ,  H01J37/321 ,  H01J2237/2001 ,  H01J2237/3341 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02321 ,  H01L21/0234 ,  H01L21/02359 ,  H01L21/31122 ,  H01L21/67069 ,  H01L21/67103 ,  H01L21/67109 ,  H01L21/6719

Abstract: A method for etching a metal oxide layer on a semiconductor substrate, comprising providing a plurality of cycles, is provided. Each cycle comprises exposing the metal oxide layer to a reactive hydrogen-containing gas or plasma to transform a part of the metal oxide layer into a layer of metal hydride, stopping the exposing the metal oxide layer to the reactive hydrogen-containing gas or plasma, heating the layer of metal hydride to at least a sublimation temperature to sublime the layer of metal hydride, and cooling the metal oxide layer to a temperature below the sublimation temperature.

公开(公告)号：US20190019683A1

公开(公告)日：2019-01-17

申请号：US16016602

申请日：2018-06-24

Applicant: SK hynix Inc.

Inventor： Hyangkeun YOO

IPC: H01L21/28 ,  H01L21/02 ,  H01L29/51 ,  H01L29/66 ,  H01L27/1159 ,  G11C11/22 ,  H01L29/78

CPC classification number: H01L29/40111 ,  G11C11/223 ,  G11C11/2273 ,  G11C11/2275 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02304 ,  H01L21/0234 ,  H01L21/02356 ,  H01L21/31155 ,  H01L27/1159 ,  H01L29/516 ,  H01L29/517 ,  H01L29/6684 ,  H01L29/78391

Abstract: A method of fabricating a ferroelectric memory device is provided. The method includes preparing a substrate, forming an interfacial insulation layer on the substrate, forming a ferroelectric layer on the interfacial insulation layer, applying a surface treatment process to the ferroelectric layer to form an oxygen vacancy region in the ferroelectric layer, forming a gate electrode layer on the ferroelectric layer, and annealing the ferroelectric layer to crystallize the ferroelectric layer.