公开(公告)号：US20120113707A1

公开(公告)日：2012-05-10

申请号：US13288089

申请日：2011-11-03

Applicant: Yasuhiko TAKEMURA

Inventor： Yasuhiko TAKEMURA

IPC: G11C11/24

CPC classification number: G11C7/1078 ,  G11C7/1048 ,  G11C11/24 ,  G11C11/40 ,  G11C11/404 ,  G11C11/405 ,  G11C16/02

Abstract: A novel semiconductor memory device whose power consumption is low is provided. A source of a writing transistor WTr_n_m, a gate of a reading transistor RTr_n_m, and one electrode of a capacitor CS_n_m are connected to each other. A gate and a drain of the writing transistor WTr_n_m are connected to a writing word line WWL_n and a writing bit line WBL_m, respectively. The other electrode of the capacitor CS_n_m is connected to a reading word line RWL_n. A drain of the reading transistor RTr_n_m is connected to a reading bit line RBL_m. Here, the potential of the reading bit line RBL_m is input to an inverting amplifier circuit such as a flip-flop circuit FF_m to be inverted by the inverting amplifier circuit. This inverted potential is output to the writing bit line WBL_m.

Abstract translation: 提供功耗低的新型半导体存储器件。 写入晶体管WTr_n_m的源极，读取晶体管RTr_n_m的栅极和电容器CS_n_m的一个电极彼此连接。 写入晶体管WTr_n_m的栅极和漏极分别连接到写入字线WWL_n和写入位线WBL_m。 电容器CS_n_m的另一个电极连接到读取字线RWL_n。 读取晶体管RTr_n_m的漏极连接到读取位线RBL_m。 这里，读出位线RBL_m的电位被输入到反相放大电路，例如触发器电路FF_m，由反相放大器电路反相。 该反相电位被输出到写入位线WBL_m。

公开(公告)号：US20120033486A1

公开(公告)日：2012-02-09

申请号：US13195089

申请日：2011-08-01

Applicant: Hiroki Inoue ,  Kiyoshi Kato ,  Takanori Matsuzaki ,  Shuhei Nagatsuka

Inventor： Hiroki Inoue ,  Kiyoshi Kato ,  Takanori Matsuzaki ,  Shuhei Nagatsuka

IPC: G11C11/24 ,  H01L27/06 ,  H01L29/04

CPC classification number: G11C16/0408 ,  G11C11/405 ,  G11C16/02

Abstract: It is an object to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied, and does not have a limitation on the number of writing operations. A semiconductor device includes a plurality of memory cells each including a transistor including a first semiconductor material, a transistor including a second semiconductor material that is different from the first semiconductor material, and a capacitor, and a potential switching circuit having a function of supplying a power supply potential to a source line in a writing period. Thus, power consumption of the semiconductor device can be sufficiently suppressed.

Abstract translation: 本发明的目的是提供一种具有新颖结构的半导体器件，其中即使在未提供电力的情况下也可以保持存储的数据，并且对写入操作的数量没有限制。 半导体器件包括多个存储单元，每个存储单元包括包括第一半导体材料的晶体管，包括与第一半导体材料不同的第二半导体材料的晶体管，以及电容器，以及电位切换电路， 在写作期间的电源供应潜力。 因此，可以充分地抑制半导体器件的功耗。

公开(公告)号：US20110286290A1

公开(公告)日：2011-11-24

申请号：US13108252

申请日：2011-05-16

Applicant: Koichiro Kamata

Inventor： Koichiro Kamata

IPC: G11C7/00

CPC classification number: G11C11/4076 ,  G11C11/404 ,  G11C16/02

Abstract: A period (inverted period) in which a high negative potential is applied to a gate of the transistor is provided between a writing period and a retention period. In the inverted period, supply of positive electric charge from the drain of the transistor to the oxide semiconductor layer is promoted. Thus, accumulation of positive electric charge in the oxide semiconductor layer or at the interface between the oxide semiconductor layer and a gate insulating film can converge in a short time. Therefore, it is possible to suppress a decrease in the positive electric charge in the node electrically connected to the drain of the transistor in the retention period after the inverted period. That is, the temporal change of data stored in the semiconductor device can be suppressed.

Abstract translation: 在写入期间和保持期间之间，设置向晶体管的栅极施加高负电位的期间（反转期间）。 在反相期间，促进了从晶体管的漏极到氧化物半导体层的正电荷的供给。 因此，在氧化物半导体层中或在氧化物半导体层和栅极绝缘膜之间的界面处的正电荷的积累可以在短时间内收敛。 因此，可以抑制在倒置时间段之后的保持期间电连接到晶体管的漏极的节点中的正电荷的减少。 也就是说，可以抑制存储在半导体器件中的数据的时间变化。

公开(公告)号：US08014200B2

公开(公告)日：2011-09-06

申请号：US12420659

申请日：2009-04-08

Applicant: Yuniarto Widjaja

Inventor： Yuniarto Widjaja

IPC: G11C11/34 ,  G11C14/00

CPC classification number: G11C14/0018 ,  G11C11/5671 ,  G11C14/00 ,  G11C16/02 ,  G11C16/0466 ,  G11C16/0475 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/115 ,  H01L29/7841 ,  H01L29/792

Abstract: A semiconductor memory cell, semiconductor memory devices comprising a plurality of the semiconductor memory cells, and methods of using the semiconductor memory cell and devices are described. A semiconductor memory cell includes a substrate having a first conductivity type; a first region embedded in the substrate at a first location of the substrate and having a second conductivity type; a second region embedded in the substrate at a second location of the substrate and have the second conductivity type, such that at least a portion of the substrate having the first conductivity type is located between the first and second locations and functions as a floating body to store data in volatile memory; a trapping layer positioned in between the first and second locations and above a surface of the substrate; the trapping layer comprising first and second storage locations being configured to store data as nonvolatile memory independently of one another; and a control gate positioned above the trapping layer.

Abstract translation: 描述了半导体存储单元，包括多个半导体存储单元的半导体存储器件以及使用该半导体存储单元和器件的方法。 半导体存储单元包括具有第一导电类型的衬底; 第一区域，其在衬底的第一位置处嵌入衬底并具有第二导电类型; 第二区域，其在衬底的第二位置处嵌入在衬底中并具有第二导电类型，使得具有第一导电类型的衬底的至少一部分位于第一和第二位置之间，并且用作浮体 将数据存储在易失性存储器中; 位于所述第一位置和所述第二位置之间并位于所述衬底的表面之上的捕获层; 所述捕获层包括第一和第二存储位置，其被配置为独立于彼此独立地存储作为非易失性存储器的数据; 以及位于捕获层上方的控制门。

公开(公告)号：US20110194332A1

公开(公告)日：2011-08-11

申请号：US13019344

申请日：2011-02-02

Applicant: Toshihiko Saito

Inventor： Toshihiko Saito

IPC: G11C11/24

CPC classification number: G11C16/02 ,  G11C11/404 ,  H01L29/94

Abstract: An object is to provide a semiconductor device capable of accurate data retention even with a memory element including a depletion mode transistor. A gate terminal of a transistor for controlling input of a signal to a signal holding portion is negatively charged in advance. The connection to a power supply is physically broken, whereby negative charge is held at the gate terminal. Further, a capacitor having terminals one of which is electrically connected to the gate terminal of the transistor is provided, and thus switching operation of the transistor is controlled with the capacitor.

Abstract translation: 目的是提供一种半导体器件，即使使用包括耗尽型晶体管的存储元件，也能够准确地保持数据保持。 用于控制信号到信号保持部分的信号的输入的晶体管的栅极端子被预先带负电。 与电源的连接物理断开，从而在门极端子处保持负电荷。 此外，提供了具有与晶体管的栅极端子电连接的端子的电容器，因此用电容器控制晶体管的开关动作。

公开(公告)号：US07995384B2

公开(公告)日：2011-08-09

申请号：US12192797

申请日：2008-08-15

Applicant: Tien-Fan Ou ,  Wen-Jer Tsai ,  Jyun-Siang Huang

Inventor： Tien-Fan Ou ,  Wen-Jer Tsai ,  Jyun-Siang Huang

IPC: G11C11/36

CPC classification number: H01L27/1021 ,  G11C11/56 ,  G11C16/02 ,  G11C17/06 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/11517 ,  H01L27/11563 ,  H01L29/66356 ,  H01L29/8616

Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Adjacent memory devices are electrically isolated. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract translation: 具有电荷存储结构的门控二极管非易失性存储单元包括具有附加栅极端子的二极管结构。 相邻的存储器件是电隔离的。 示例性实施例包括单独的存储器单元，这种存储器单元的阵列，操作存储单元或存储单元阵列的方法及其制造方法。

公开(公告)号：US20110128767A1

公开(公告)日：2011-06-02

申请号：US12627751

申请日：2009-11-30

Applicant: Cyrille Dray

Inventor： Cyrille Dray

IPC: G11C5/06 ,  H01L27/105

CPC classification number: G11C16/02 ,  G11C8/14

Abstract: Disclosed herein are memory devices and related methods and techniques. A cell in the memory device may be associated with an intervening transistor, the intervening transistor being configured to isolate the cell from adjacent cells under a first operating condition and to provide a current to a bit line associated with the cell under a second operating condition.

Abstract translation: 这里公开的是存储器件和相关的方法和技术。 存储器件中的单元可以与中间晶体管相关联，所述中间晶体管被配置为在第一操作条件下隔离所述单元与相邻单元，并且在第二操作条件下向与所述单元相关联的位线提供电流。

公开(公告)号：US20110101334A1

公开(公告)日：2011-05-05

申请号：US12912190

申请日：2010-10-26

Applicant: Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

IPC: H01L27/108

CPC classification number: H01L27/088 ,  G11C11/404 ,  G11C11/405 ,  G11C16/02 ,  H01L27/0207 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/1156 ,  H01L27/1225

Abstract: It is an object to provide a semiconductor having a novel structure. In the semiconductor device, a plurality of memory elements are connected in series and each of the plurality of memory elements includes first to third transistors thus forming a memory circuit. A source or a drain of a first transistor which includes an oxide semiconductor layer is in electrical contact with a gate of one of a second and a third transistor. The extremely low off current of a first transistor containing the oxide semiconductor layer allows storing, for long periods of time, electrical charges in the gate electrode of one of the second and the third transistor, whereby a substantially permanent memory effect can be obtained. The second and the third transistors which do not contain an oxide semiconductor layer allow high-speed operations when using the memory circuit.

Abstract translation: 本发明的目的是提供具有新颖结构的半导体。 在半导体器件中，多个存储器元件串联连接，并且多个存储元件中的每一个包括第一至第三晶体管，从而形成存储器电路。 包括氧化物半导体层的第一晶体管的源极或漏极与第二和第三晶体管之一的栅极电接触。 含有氧化物半导体层的第一晶体管的极低的截止电流允许长时间地在第二和第三晶体管之一的栅电极中存储电荷，由此可以获得基本上永久的记忆效应。 不含氧化物半导体层的第二和第三晶体管在使用存储电路时允许高速操作。

公开(公告)号：US20110101332A1

公开(公告)日：2011-05-05

申请号：US12910908

申请日：2010-10-25

Applicant: Shunpei YAMAZAKI ,  Keitaro IMAI ,  Jun KOYAMA

Inventor： Shunpei YAMAZAKI ,  Keitaro IMAI ,  Jun KOYAMA

IPC: H01L29/12

CPC classification number: H01L27/10802 ,  G11C11/404 ,  G11C11/405 ,  G11C16/02 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0922 ,  H01L27/105 ,  H01L27/1156 ,  H01L27/12 ,  H01L27/1225 ,  H01L29/7869

Abstract: The semiconductor device includes: a transistor having an oxide semiconductor layer; and a logic circuit formed using a semiconductor material other than an oxide semiconductor. One of a source electrode and a drain electrode of the transistor is electrically connected to at least one input of the logic circuit, and at least one input signal is applied to the logic circuit through the transistor. The off-current of the transistor is preferably 1×10−13 A or less.

Abstract translation: 半导体器件包括：具有氧化物半导体层的晶体管; 以及使用除了氧化物半导体之外的半导体材料形成的逻辑电路。 晶体管的源电极和漏电极中的一个电连接到逻辑电路的至少一个输入端，并且至少一个输入信号通过晶体管施加到逻辑电路。 晶体管的截止电流优选为1×10-13A以下。

公开(公告)号：US07888707B2

公开(公告)日：2011-02-15

申请号：US11923069

申请日：2007-10-24

Applicant: Yi Ying Liao ,  Wen Jer Tsai ,  Chih Chieh Yeh

Inventor： Yi Ying Liao ,  Wen Jer Tsai ,  Chih Chieh Yeh

IPC: H01L23/52

CPC classification number: G11C8/10 ,  B82Y10/00 ,  G11C11/36 ,  G11C16/02 ,  G11C2216/06 ,  H01L27/1021 ,  H01L27/115 ,  H01L29/7391 ,  H01L29/8616

Abstract: A gated diode nonvolatile memory cell with a charge storage structure includes a diode structure with an additional gate terminal. Example embodiments include the individual memory cell, an array of such memory cells, methods of operating the memory cell or array of memory cells, and methods of manufacturing the same.

Abstract translation: 具有电荷存储结构的门控二极管非易失性存储单元包括具有附加栅极端子的二极管结构。 示例性实施例包括单独的存储器单元，这种存储器单元的阵列，操作存储单元或存储单元阵列的方法及其制造方法。