公开(公告)号：US20120001168A1

公开(公告)日：2012-01-05

申请号：US13164806

申请日：2011-06-21

Applicant: Mitsuhiro ICHIJO ,  Toshiya ENDO ,  Kunihiko SUZUKI ,  Yasuhiko TAKEMURA

Inventor： Mitsuhiro ICHIJO ,  Toshiya ENDO ,  Kunihiko SUZUKI ,  Yasuhiko TAKEMURA

IPC: H01L29/786

CPC classification number: H01L29/7869

Abstract: In a transistor including an oxide semiconductor, hydrogen in the oxide semiconductor leads to degradation of electric characteristics of the transistor. Thus, an object is to provide a semiconductor device having good electrical characteristics. An insulating layer in contact with an oxide semiconductor layer where a channel region is formed is formed by a plasma CVD method using a silicon halide. The insulating layer thus formed has a hydrogen concentration less than 6×1020 atoms/cm3 and a halogen concentration greater than or equal to 1×1020 atoms/cm3; accordingly, hydrogen diffusion into the oxide semiconductor layer can be prevented and hydrogen in the oxide semiconductor layer is inactivated or released from the oxide semiconductor layer by the halogen, whereby a semiconductor device having good electrical characteristics can be provided.

Abstract translation: 在包括氧化物半导体的晶体管中，氧化物半导体中的氢导致晶体管的电特性的劣化。 因此，目的在于提供具有良好的电气特性的半导体器件。 通过使用卤化硅的等离子体CVD法形成与形成沟道区的氧化物半导体层接触的绝缘层。 如此形成的绝缘层的氢浓度小于6×1020原子/ cm3，卤素浓度大于或等于1×1020原子/ cm3; 因此，可以防止氢扩散到氧化物半导体层中，并且氧化物半导体层中的氢被卤素氧化半导体层失活或释放，从而可以提供具有良好电特性的半导体器件。

公开(公告)号：US20110068339A1

公开(公告)日：2011-03-24

申请号：US12958739

申请日：2010-12-02

Applicant: Toshimitsu KONUMA ,  Akira SUGAWARA ,  Yukiko UEHARA ,  Hongyong ZHANG ,  Atsunori SUZUKI ,  Hideto OHNUMA ,  Naoaki YAMAGUCHI ,  Hideomi SUZAWA ,  Hideki UOCHI ,  Yasuhiko TAKEMURA

Inventor： Toshimitsu KONUMA ,  Akira SUGAWARA ,  Yukiko UEHARA ,  Hongyong ZHANG ,  Atsunori SUZUKI ,  Hideto OHNUMA ,  Naoaki YAMAGUCHI ,  Hideomi SUZAWA ,  Hideki UOCHI ,  Yasuhiko TAKEMURA

IPC: H01L29/772 ,  H01L27/12

CPC classification number: H01L29/665 ,  H01L21/02145 ,  H01L21/02244 ,  H01L21/02258 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/31683 ,  H01L21/31687 ,  H01L21/321 ,  H01L27/124 ,  H01L27/127 ,  H01L29/458 ,  H01L29/66598 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627

Abstract: A TFT formed on an insulating substrate source, drain and channel regions, a gate insulating film formed on at least the channel region and a gate electrode formed on the gate insulating film. Between the channel region and the drain region, a region having a higher resistivity is provided in order to reduce an Ioff current. A method for forming this structure comprises the steps of anodizing the gate electrode to form a porous anodic oxide film on the side of the gate electrode; removing a portion of the gate insulating using the porous anodic oxide film as a mask so that the gate insulating film extends beyond the gate electrode but does not completely cover the source and drain regions. Thereafter, an ion doping of one conductivity element is performed. The high resistivity region is defined under the gate insulating film.

Abstract translation: 形成在绝缘基板源极，漏极和沟道区上的TFT，至少形成在沟道区上的栅极绝缘膜和形成在栅极绝缘膜上的栅电极。 在沟道区域和漏极区域之间，提供具有较高电阻率的区域以便减小偏转电流。 形成该结构的方法包括以下步骤：在栅电极侧阳极氧化栅电极以形成多孔阳极氧化膜; 使用多孔阳极氧化膜去除一部分栅极绝缘体作为掩模，使得栅极绝缘膜延伸超过栅极电极但不完全覆盖源极和漏极区域。 此后，进行一个导电性元素的离子掺杂。 高电阻率区域限定在栅极绝缘膜下。

公开(公告)号：US20120287700A1

公开(公告)日：2012-11-15

申请号：US13461807

申请日：2012-05-02

Applicant: Yasuhiko TAKEMURA

Inventor： Yasuhiko TAKEMURA

IPC: G11C11/24

CPC classification number: H01L27/0688 ,  G11C11/405 ,  H01L27/108 ,  H01L27/1207

Abstract: A memory cell including two transistors and one capacitor, which is known as a gain cell, is improved. One electrode of the capacitor is connected to a bit line, and the other electrode thereof is connected to a drain of a write transistor. A source of the write transistor is connected to a source line. As a result, for example, in the case where a stacked capacitor is used, the one electrode of the capacitor can be part of the bit line. Only one specific write transistor is turned on when a potential of the source line and a potential of the write bit line are set; thus, only one memory cell can be rewritten.

Abstract translation: 改进了包括两个晶体管和一个电容器的存储单元，这被称为增益单元。 电容器的一个电极连接到位线，并且其另一个电极连接到写入晶体管的漏极。 写入晶体管的源极连接到源极线。 结果，例如，在使用层叠电容器的情况下，电容器的一个电极可以是位线的一部分。 当源极线的电位和写入位线的电位被置位时，只有一个特定的写入晶体管导通; 因此，只能重写一个存储单元。

公开(公告)号：US20120257440A1

公开(公告)日：2012-10-11

申请号：US13440227

申请日：2012-04-05

Applicant: Yasuhiko TAKEMURA

Inventor： Yasuhiko TAKEMURA

IPC: G11C11/24

CPC classification number: G11C27/024 ,  G11C5/10 ,  G11C11/24 ,  G11C11/41 ,  G11C11/412

Abstract: An object is to provide a memory device for which a complex manufacturing process is not necessary and whose power consumption can be suppressed, and a signal processing circuit including the memory device. In a memory element including a phase-inversion element such as an inverter or a clocked inverter, a capacitor which holds data and a switching element which controls storing and releasing of electric charge in the capacitor are provided. For the above switching element, a transistor including amorphous silicon, polysilicon, microcrystalline silicon, or a compound semiconductor such as an oxide semiconductor in a channel formation region is used. The channel length of the transistor is ten times or more as large as the minimum feature size or greater than or equal to 1 μm. The above memory element is used for a memory device such as a register or a cache memory in the signal processing circuit.

Abstract translation: 本发明的目的是提供一种不需要复杂制造处理并且可以抑制其功耗的存储器件，以及包括存储器件的信号处理电路。 在包括诸如逆变器或时钟反相器的相位反转元件的存储元件中，提供保持数据的电容器和控制电容器中的电荷的存储和释放的开关元件。 对于上述开关元件，使用在沟道形成区域中包括非晶硅，多晶硅，微晶硅或化合物半导体如氧化物半导体的晶体管。 晶体管的沟道长度是最小特征尺寸的10倍以上，或大于或等于1μm。 上述存储元件用于信号处理电路中的诸如寄存器或高速缓冲存储器之类的存储器件。

公开(公告)号：US20120217486A1

公开(公告)日：2012-08-30

申请号：US13405384

申请日：2012-02-27

Applicant: Yasuhiko TAKEMURA ,  Shunpei YAMAZAKI

Inventor： Yasuhiko TAKEMURA ,  Shunpei YAMAZAKI

IPC: H01L51/52 ,  B82Y20/00

CPC classification number: B82Y20/00 ,  H01L51/5012 ,  H01L2251/552 ,  H01L2251/558

Abstract: To provide a highly efficient organic light-emitting element. An extremely thin layer (a monomolecular film or the like) containing an organic light-emitting material such as an iridium complex is provided between a layer of an n-type organic material (an organic material having a high electron-transport property) and a layer of a p-type organic material (an organic material having a high hole-transport property). In a structure described above, in a layer of the organic light-emitting material, electrons are injected from the LUMO of the n-type organic material to the LUMO of the organic light-emitting material, and holes are injected from the HOMO of the p-type organic material to the HOMO of the organic light-emitting material, whereby the organic light-emitting material is brought into an excited state and emits light.

Abstract translation: 提供高效的有机发光元件。 在n型有机材料（具有高电子传输性的有机材料）的层和一层有机发光材料之间设置包含铱络合物等有机发光材料的极薄层（单分子膜等） p型有机材料（具有高空穴传输性的有机材料）层。 在上述结构中，在有机发光材料的层中，电子从n型有机材料的LUMO注入有机发光材料的LUMO，从HOMO的 p型有机材料发送到有机发光材料的HOMO，由此有机发光材料进入激发状态并发光。

公开(公告)号：US20110279419A1

公开(公告)日：2011-11-17

申请号：US13100808

申请日：2011-05-04

Applicant: Yasuhiko TAKEMURA

Inventor： Yasuhiko TAKEMURA

IPC: G09G5/00 ,  G09G3/30

CPC classification number: G09G3/3659 ,  G09G2300/0417 ,  G09G2300/0823 ,  G09G2300/0861

Abstract: A method of reducing power consumption of an electro-optical display device which can display a still image with the use of analog signals. A circuit in which low leakage current flows between a source and a drain of a selection transistor when the selection transistor is off; the source of the selection transistor is connected to a gate of a first driving transistor, a gate of a second driving transistor, and one electrode of a display element; and a source of the second driving transistor is connected to the other electrode of the display element is provided in each pixel. A gate and the drain of the selection transistor are connected to a scan line and a signal line, respectively. A drain of the first driving transistor is connected to a first power supply line. A drain of the second driving transistor is connected to a second power supply line.

Abstract translation: 一种降低能够使用模拟信号显示静止图像的电光显示装置的功耗的方法。 当选择晶体管截止时，在选择晶体管的源极和漏极之间流过低漏电流的电路; 选择晶体管的源极连接到第一驱动晶体管的栅极，第二驱动晶体管的栅极和显示元件的一个电极; 并且在每个像素中设置与显示元件的另一个电极连接的第二驱动晶体管的源极。 选择晶体管的栅极和漏极分别连接到扫描线和信号线。 第一驱动晶体管的漏极连接到第一电源线。 第二驱动晶体管的漏极连接到第二电源线。

公开(公告)号：US20110205774A1

公开(公告)日：2011-08-25

申请号：US13024401

申请日：2011-02-10

Applicant: Yasuhiko TAKEMURA

Inventor： Yasuhiko TAKEMURA

IPC: G11C5/10 ,  G11C11/40 ,  H01L21/336 ,  H01L29/94

CPC classification number: H01L27/115 ,  G11C16/0408 ,  H01L27/0629 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/1156 ,  H01L27/1225

Abstract: A matrix is formed using a plurality of memory cells in each of which a drain of the writing transistor is connected to a gate of a reading transistor and one electrode of a capacitor. A gate of the writing transistor, a source of the writing transistor, a source of the reading transistor, and a drain of the reading transistor are connected to a writing word line, a writing bit line, a reading bit line, and a bias line, respectively. The other electrode of the capacitor is connected to a reading word line. In order to decrease the number of wirings, the writing bit line is substituted for the reading bit line. The reading bit line is formed so as to be embedded in a groove-like opening formed over a substrate.

Abstract translation: 使用多个存储单元形成矩阵，每个存储单元中的写入晶体管的漏极连接到读取晶体管的栅极和电容器的一个电极。 写入晶体管的栅极，写入晶体管的源极，读取晶体管的源极和读取晶体管的漏极连接到写入字线，写入位线，读取位线和偏置线 ， 分别。 电容器的另一个电极连接到读取字线。 为了减少布线数量，写入位线代替读取位线。 读取位线形成为嵌入形成在基板上的槽状开口。

公开(公告)号：US20110111541A1

公开(公告)日：2011-05-12

申请号：US13010087

申请日：2011-01-20

Applicant: Yasuhiko TAKEMURA

Inventor： Yasuhiko TAKEMURA

IPC: H01L21/336

CPC classification number: H01L21/02672 ,  H01L21/02422 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02667 ,  H01L27/12 ,  H01L27/1277 ,  H01L27/1285 ,  H01L29/04 ,  H01L29/66757 ,  H01L29/78675 ,  Y10S438/982

Abstract: A silicon film is crystallized in a predetermined direction by selectively adding a metal element having a catalytic action for crystallizing an amorphous silicon and annealing. In manufacturing TFT using the crystallized silicon film, TFT provided such that the crystallization direction is roughly parallel to a current-flow between a source and a drain, and TFT provided such that the crystallization direction is roughly vertical to a current-flow between a source and a drain are manufactured. Therefore, TFT capable of conducting a high speed operation and TFT having a low leak current are formed on the same substrate.

Abstract translation: 通过选择性地添加具有用于结晶非晶硅的催化作用的金属元素和退火，使硅膜沿预定方向结晶。 在制造使用结晶硅膜的TFT中，TFT被提供为使得结晶方向大致平行于源极和漏极之间的电流，并且TFT被设置为使得结晶方向大致垂直于源极之间的电流 并制造漏极。 因此，能够进行高速运算的TFT和具有低漏电流的TFT形成在同一基板上。

公开(公告)号：US20110081769A1

公开(公告)日：2011-04-07

申请号：US12897045

申请日：2010-10-04

Applicant: Yasuhiko TAKEMURA

Inventor： Yasuhiko TAKEMURA

IPC: H01L21/18

CPC classification number: H01L27/1266 ,  H01L27/1214 ,  H01L27/1251 ,  H01L29/66772

Abstract: A chip provided with a layer for separation of a surface region and a hydrophilic surface is manufactured. One or both of a hydrophilic region and a hydrophobic region are formed on a substrate surface where the chip is placed. Liquid is dropped onto the hydrophilic region on the substrate surface, and the chip is placed thereon. The substrate and the chip are heated while being pressure-bonded so that the chip is fixed on the substrate surface, and then the surface region of the chip is separated. By providing a liquid layer in a position where the chip is placed, the chip can be placed on the substrate with high accuracy and thus productivity can be increased.

Abstract translation: 制造具有用于分离表面区域和亲水表面的层的芯片。 在放置芯片的基板表面上形成亲水区域和疏水区域中的一个或两个。 将液体滴落到基板表面上的亲水区域上，并且将芯片放置在其上。 将衬底和芯片加压加压，使得芯片固定在衬底表面上，然后将芯片的表面区域分离。 通过在放置芯片的位置提供液体层，可以高精度地将芯片放置在基板上，从而可以提高生产率。

公开(公告)号：US20100068860A1

公开(公告)日：2010-03-18

申请号：US12621537

申请日：2009-11-19

Applicant: Hongyong ZHANG ,  Yasuhiko TAKEMURA ,  Toshimitsu KONUMA ,  Hideto OHNUMA ,  Naoaki YAMAGUCHI ,  Hideomi SUZAWA ,  Hideki UOCHI

Inventor： Hongyong ZHANG ,  Yasuhiko TAKEMURA ,  Toshimitsu KONUMA ,  Hideto OHNUMA ,  Naoaki YAMAGUCHI ,  Hideomi SUZAWA ,  Hideki UOCHI

IPC: H01L21/336

CPC classification number: H01L27/127 ,  H01L27/1214 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78627

Abstract: There is provided a method by which lightly doped drain (LDD) regions can be formed easily and at good yields in source/drain regions in thin film transistors possessing gate electrodes covered with an oxide covering. A lightly doped drain (LDD) region is formed by introducing an impurity into an island-shaped silicon film in a self-aligning manner, with a gate electrode serving as a mask. First, low-concentration impurity regions are formed in the island-shaped silicon film by using rotation-tilt ion implantation to effect ion doping from an oblique direction relative to the substrate. Low-concentration impurity regions are also formed below the gate electrode at this time. After that, an impurity at a high concentration is introduced normally to the substrate, so forming high-concentration impurity regions. In the above process, a low-concentration impurity region remains below the gate electrode and constitutes a lightly doped drain region.

Abstract translation: 提供了一种方法，通过该方法可以容易地形成轻掺杂漏极（LDD）区域，并且在具有覆盖有氧化物覆盖层的栅电极的薄膜晶体管中的源/漏区域中以良好的产率形成。 通过以栅极电极作为掩模，以自对准的方式将杂质引入岛状硅膜中形成轻掺杂漏极（LDD）区域。 首先，通过使用旋转 - 倾斜离子注入在岛状硅膜中形成低浓度杂质区，以相对于衬底从倾斜方向进行离子掺杂。 此时也在栅电极下方形成低浓度杂质区。 之后，将高浓度的杂质通常引入衬底，从而形成高浓度杂质区域。 在上述过程中，低浓度杂质区域保留在栅电极下方并构成轻掺杂漏区。