公开(公告)号：US09130051B2

公开(公告)日：2015-09-08

申请号：US13402212

申请日：2012-02-22

申请人： Hideto Ohnuma ,  Atsuo Isobe ,  Hiromichi Godo

发明人： Hideto Ohnuma ,  Atsuo Isobe ,  Hiromichi Godo

IPC分类号： H01L29/786 ,  H01L27/12 ,  H01L21/02

CPC分类号： H01L29/78696 ,  H01L21/0237 ,  H01L21/02675 ,  H01L21/02691 ,  H01L27/1281

摘要： A semiconductor device having a highly responsive thin film transistor (TFT) with low subthreshold swing and suppressed decrease in the on-state current and a manufacturing method thereof are demonstrated. The TFT of the present invention is characterized by its semiconductor layer where the thickness of the source region or the drain region is larger than that of the channel formation region. Manufacture of the TFT is readily achieved by the formation of an amorphous semiconductor layer on a projection portion and a depression portion, which is followed by subjecting the melting process of the semiconductor layer, resulting in the formation of a crystalline semiconductor layer having different thicknesses. Selective addition of impurity to the thick portion of the semiconductor layer provides a semiconductor layer in which the channel formation region is thinner than the source or drain region.

摘要翻译： 示出了具有低亚阈值摆动和抑制导通电流下降的高响应性薄膜晶体管（TFT）的半导体器件及其制造方法。 本发明的TFT的特征在于其源极区域或漏极区域的厚度大于沟道形成区域的厚度的半导体层。 通过在突起部分和凹陷部分上形成非晶半导体层来容易地实现TFT的制造，随后对半导体层进行熔化处理，形成具有不同厚度的晶体半导体层。 选择性地向半导体层的厚部分添加杂质提供了沟道形成区域比源区或漏区更薄的半导体层。

公开(公告)号：US08985173B2

公开(公告)日：2015-03-24

申请号：US13110950

申请日：2011-05-19

申请人： Takatsugu Omata ,  Tomoaki Moriwaka ,  Hideto Ohnuma

发明人： Takatsugu Omata ,  Tomoaki Moriwaka ,  Hideto Ohnuma

IPC分类号： B32B37/00 ,  H01L21/18 ,  H01L21/762

CPC分类号： H01L21/187 ,  H01L21/76254 ,  Y10T156/17

摘要： It is an object to provide a homogeneous semiconductor substrate in which defective bonding is reduced. Such a semiconductor substrate can be formed by the steps of: disposing a first substrate in a substrate bonding chamber which includes a substrate supporting base where a plurality of openings is provided, substrate supporting mechanisms provided in the plurality of openings, and raising and lowering mechanisms which raise and lower the substrate supporting mechanisms; disposing a second substrate over the first substrate so as not to be in contact with the first substrate; and bonding the first substrate to the second substrate by using the raising and lowering mechanisms to raise the substrate supporting mechanisms.

摘要翻译： 本发明的目的是提供一种均匀的半导体衬底，其中不良接合被降低。 这样的半导体基板可以通过以下步骤形成：将第一基板设置在基板接合室中，该基板接合室包括设置有多个开口的基板支撑基座，设置在多个开口中的基板支撑机构，以及升降机构 其升高和降低基板支撑机构; 将第二基板设置在所述第一基板上以不与所述第一基板接触; 以及通过使用升高和降低机构来将第一基板结合到第二基板以升高基板支撑机构。

公开(公告)号：US08828844B2

公开(公告)日：2014-09-09

申请号：US12247487

申请日：2008-10-08

申请人： Hideto Ohnuma ,  Tetsuya Kakehata ,  Akihisa Shimomura ,  Shinya Sasagawa ,  Motomu Kurata

发明人： Hideto Ohnuma ,  Tetsuya Kakehata ,  Akihisa Shimomura ,  Shinya Sasagawa ,  Motomu Kurata

IPC分类号： H01L21/46 ,  H01L21/268 ,  H01L21/3065 ,  H01L21/84 ,  H01L21/02 ,  H01L21/302 ,  H01L21/762

CPC分类号： H01L21/76254 ,  H01L21/02532 ,  H01L21/02686 ,  H01L21/268 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/84

摘要： A damaged region is formed by generation of plasma by excitation of a source gas, and by addition of ion species contained in the plasma from one of surfaces of a single crystal semiconductor substrate; an insulating layer is formed over the other surface of the single crystal semiconductor substrate; a supporting substrate is firmly attached to the single crystal semiconductor substrate so as to face the single crystal semiconductor substrate with the insulating layer interposed therebetween; separation is performed at the damaged region into the supporting substrate to which a single crystal semiconductor layer is attached and part of the single crystal semiconductor substrate by heating of the single crystal semiconductor substrate; dry etching is performed on a surface of the single crystal semiconductor layer attached to the supporting substrate; the single crystal semiconductor layer is recrystallized by irradiation of the single crystal semiconductor layer with a laser beam to melt at least part of the single crystal semiconductor layer.

摘要翻译： 通过源气体的激发产生等离子体并通过从单晶半导体衬底的表面之一添加包含在等离子体中的离子种类而形成损伤区域; 在单晶半导体衬底的另一个表面上形成绝缘层; 支撑衬底牢固地附接到单晶半导体衬底，以便在其间插入绝缘层的单晶半导体衬底; 通过加热单晶半导体衬底，在损伤区域处分离成与单晶半导体层相连的支撑衬底和部分单晶半导体衬底; 在附着于支撑基板的单晶半导体层的表面进行干蚀刻， 通过用激光束照射单晶半导体层来使单晶半导体层重结晶，从而熔化至少一部分单晶半导体层。

公开(公告)号：US08823063B2

公开(公告)日：2014-09-02

申请号：US13267024

申请日：2011-10-06

申请人： Hideto Ohnuma ,  Tetsuya Kakehata ,  Yoichi Iikubo

发明人： Hideto Ohnuma ,  Tetsuya Kakehata ,  Yoichi Iikubo

IPC分类号： H01L29/772 ,  H01L29/04

CPC分类号： H01L21/76254 ,  H01L21/84

摘要： An SOI substrate having an SOI layer that can be used in practical applications even when a substrate with low upper temperature limit, such as a glass substrate, is used, is provided. A semiconductor device using such an SOI substrate, is provided. In bonding a single-crystal semiconductor layer to a substrate having an insulating surface or an insulating substrate, a silicon oxide film formed using organic silane as a material on one or both surfaces that are to form a bond is used. According to the present invention, a substrate with an upper temperature limit of 700° C. or lower, such as a glass substrate, can be used, and an SOI layer that is strongly bonded to the substrate can be obtained. In other words, a single-crystal semiconductor layer can be formed over a large-area substrate that is longer than one meter on each side.

摘要翻译： 提供了即使使用诸如玻璃基板的具有低的上限温度的基板也可以在实际应用中使用具有SOI层的SOI衬底。 提供了使用这种SOI衬底的半导体器件。 在将单晶半导体层接合到具有绝缘表面的基板或绝缘基板上时，使用在有一个或两个表面上形成键的有机硅烷作为材料形成的氧化硅膜。 根据本发明，可以使用具有700℃以上的上限温度的基板，例如玻璃基板，并且可以获得与基板强结合的SOI层。 换句话说，单晶半导体层可以形成在每侧长于1米的大面积基板上。

公开(公告)号：US08658508B2

公开(公告)日：2014-02-25

申请号：US13411864

申请日：2012-03-05

申请人： Takeshi Shichi ,  Junichi Koezuka ,  Hideto Ohnuma ,  Shunpei Yamazaki

发明人： Takeshi Shichi ,  Junichi Koezuka ,  Hideto Ohnuma ,  Shunpei Yamazaki

IPC分类号： H01L21/33 ,  H01L21/8222

CPC分类号： H01L27/1266 ,  H01L21/76254 ,  H01L27/1214 ,  H01L29/66772

摘要： The present invention provides a method for manufacturing an SOI substrate, to improve planarity of a surface of a single crystal semiconductor layer after separation by favorably separating a single crystal semiconductor substrate even in the case where a non-mass-separation type ion irradiation method is used, and to improve planarity of a surface of a single crystal semiconductor layer after separation as well as to improve throughput. The method includes the steps of irradiating a single crystal semiconductor substrate with accelerated ions by an ion doping method while the single crystal semiconductor substrate is cooled to form an embrittled region in the single crystal semiconductor substrate; bonding the single crystal semiconductor substrate and a base substrate with an insulating layer interposed therebetween; and separating the single crystal semiconductor substrate along the embrittled region to form a single crystal semiconductor layer over the base substrate with the insulating layer interposed therebetween.

摘要翻译： 本发明提供一种制造SOI衬底的方法，即使在非质量分离型离子照射方法为非质子分离型离子照射方法的情况下，通过有利地分离单晶半导体衬底来提高分离后的单晶半导体层的表面的平面性 并且在分离之后提高单晶半导体层的表面的平面性以及提高生产量。 该方法包括以下步骤：当单晶半导体衬底被冷却以在单晶半导体衬底中形成脆化区域时，通过离子掺杂方法照射具有加速离子的单晶半导体衬底; 将单晶半导体衬底和基底衬底之间插入绝缘层; 并且沿着脆化区域分离单晶半导体衬底，以在基底衬底上形成绝缘层，形成单晶半导体层。

公开(公告)号：US08558241B2

公开(公告)日：2013-10-15

申请号：US13609915

申请日：2012-09-11

申请人： Shunpei Yamazaki ,  Satoshi Murakami ,  Jun Koyama ,  Yukio Tanaka ,  Hidehito Kitakado ,  Hideto Ohnuma

发明人： Shunpei Yamazaki ,  Satoshi Murakami ,  Jun Koyama ,  Yukio Tanaka ,  Hidehito Kitakado ,  Hideto Ohnuma

IPC分类号： H01L27/14

CPC分类号： G02F1/1368 ,  G02F1/133345 ,  G02F1/13454 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2201/123 ,  G02F2202/104 ,  H01L27/12 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1259 ,  H01L27/3248 ,  H01L27/3258 ,  H01L27/3262 ,  H01L27/3272 ,  H01L27/3276 ,  H01L29/458 ,  H01L29/78621 ,  H01L29/78627 ,  H01L29/78675 ,  H01L2029/7863 ,  H01L2227/323

摘要： This invention provides a semiconductor device having high operation performance and high reliability. An LDD region 707 overlapping with a gate wiring is arranged in an n-channel TFT 802 forming a driving circuit, and a TFT structure highly resistant to hot carrier injection is achieved. LDD regions 717, 718, 719 and 720 not overlapping with a gate wiring are arranged in an n-channel TFT 804 forming a pixel unit. As a result, a TFT structure having a small OFF current value is achieved. In this instance, an element belonging to the Group 15 of the Periodic Table exists in a higher concentration in the LDD region 707 than in the LDD regions 717, 718, 719 and 720.

公开(公告)号：US08557676B2

公开(公告)日：2013-10-15

申请号：US12986582

申请日：2011-01-07

申请人： Shunpei Yamazaki ,  Hideto Ohnuma

发明人： Shunpei Yamazaki ,  Hideto Ohnuma

IPC分类号： H01L21/20

CPC分类号： H01L21/2007 ,  H01L21/76254

摘要： A first substrate of single-crystal silicon within which is formed an embrittled layer and over a surface of which is formed a first insulating film is provided; a second insulating film is formed over a surface of a second substrate; at least one surface of either the first insulating film or the second insulating film is exposed to a plasma atmosphere or an ion atmosphere, and that surface of the first insulating film or the second insulating film is activated; the first substrate and the second substrate are bonded together with the first insulating film and the second insulating film interposed therebetween; a single-crystal silicon film is separated from the first substrate at an interface of the embrittled layer of the first substrate, and a thin film single-crystal silicon film is formed over the second substrate with the first insulating film and the second insulating film interposed therebetween.

摘要翻译： 提供了单晶硅的第一基板，其中形成有脆化层，并且其表面上形成有第一绝缘膜; 在第二基板的表面上形成第二绝缘膜; 第一绝缘膜或第二绝缘膜的至少一个表面暴露于等离子体气氛或离子气氛中，并且第一绝缘膜或第二绝缘膜的表面被激活; 第一基板和第二基板与第一绝缘膜和第二绝缘膜接合在一起; 在第一衬底的脆化层的界面处将单晶硅膜与第一衬底分离，并且在第二衬底上形成薄膜单晶硅膜，其中第一绝缘膜和第二绝缘膜插入 之间。

公开(公告)号：US08518797B2

公开(公告)日：2013-08-27

申请号：US12212990

申请日：2008-09-18

申请人： Hideto Ohnuma ,  Shunpei Yamazaki

发明人： Hideto Ohnuma ,  Shunpei Yamazaki

IPC分类号： H01L21/46

CPC分类号： H01L21/76254

摘要： The method includes steps of adding first ions to a predetermined depth from a main surface of a semiconductor substrate by irradiation of the semiconductor substrate with a planar, linear, or rectangular ion beam, so that a separation layer is formed; adding second ions to part of the separation layer formed in the semiconductor substrate; disposing the main surface of the semiconductor substrate and a main surface of a base substrate to face each other in order to bond a surface of an insulating film and the base substrate; and cleaving the semiconductor substrate using the separation layer as a cleavage plane, so that a single crystal semiconductor layer is formed over the base substrate. The mass number of the second ions is the same as or larger than that of the first ions.

摘要翻译： 该方法包括以下步骤：通过用平面，线性或矩形离子束照射半导体衬底，从半导体衬底的主表面加入第一离子至预定深度，从而形成分离层; 向形成在半导体衬底中的分离层的一部分添加第二离子; 将半导体基板的主表面和基底基板的主表面设置为彼此面对以便将绝缘膜和基底的表面粘合; 并使用分离层将半导体衬底切割为解理面，从而在基底衬底上形成单晶半导体层。 第二离子的质量数与第一离子的质量数相同或者更大。

公开(公告)号：US08441185B2

公开(公告)日：2013-05-14

申请号：US11545910

申请日：2006-10-11

申请人： Hideaki Kuwabara ,  Hideto Ohnuma

发明人： Hideaki Kuwabara ,  Hideto Ohnuma

IPC分类号： H01L29/04 ,  H01L29/06

CPC分类号： H01L51/56 ,  H01L27/3241 ,  H01L27/3246 ,  H01L27/3258 ,  H01L27/3262 ,  H01L33/36 ,  H01L51/0011 ,  H01L51/52 ,  H01L2251/5338

摘要： As a result of miniaturization of a pixel region associated with an improvement in definition and an increase in a substrate size associated with an increase in area, defects due to precision, bending, and the like of a mask used at the time of evaporation have become issues. A partition including portions with different thicknesses over a pixel electrode (also referred to as a first electrode) in a display region and in the vicinity of a pixel electrode layer is formed, without increasing the number of steps, by using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function made of a diffraction grating pattern or a semi-transmissive film.

摘要翻译： 由于与清晰度的改善相关联的像素区域的小型化以及与面积的增加相关联的基板尺寸的增加，由于在蒸发时使用的掩模的精度，弯曲等的缺陷已经变成 问题 通过使用光掩模或掩模版形成在显示区域和像素电极层附近的像素电极（也称为第一电极）上具有不同厚度的部分，而不增加步骤数 具有由衍射光栅图案或半透射膜构成的具有光强度降低功能的辅助图案。

公开(公告)号：US08409966B2

公开(公告)日：2013-04-02

申请号：US13177584

申请日：2011-07-07

申请人： Hideto Ohnuma ,  Shunpei Yamazaki

发明人： Hideto Ohnuma ,  Shunpei Yamazaki

IPC分类号： H01L21/22 ,  H01L21/38

CPC分类号： H01L21/76254 ,  H01L21/302

摘要： A method is demonstrated to manufacture SOI substrates with high throughput while resources can be effectively used. The present invention is characterized by the feature in which the following process A and process B are repeated. The process A includes irradiation of a surface of a semiconductor wafer with cluster ions to form a separation layer in the semiconductor wafer. The semiconductor wafer and a substrate having an insulating surface are then overlapped with each other and bonded, which is followed by thermal treatment to separate the semiconductor wafer at or around the separation layer. A separation wafer and an SOT substrate which has a crystalline semiconductor layer over the substrate having the insulating surface are simultaneously obtained by the process A. The process B includes treatment of the separation wafer for reusing, which allows the separation wafer to be successively subjected to the process A.

摘要翻译： 一种方法被证明可以制造具有高产量的SOI衬底，同时可以有效地利用资源。 本发明的特征在于重复以下处理A和方法B. 方法A包括用聚簇离子照射半导体晶片的表面以在半导体晶片中形成分离层。 然后将半导体晶片和具有绝缘表面的基板彼此重叠并结合，然后进行热处理以在分离层处或周围分离半导体晶片。 通过方法A同时获得在具有绝缘表面的基板上具有结晶半导体层的分离晶片和SOT基板。工艺B包括处理用于再利用的分离晶片，其允许分离晶片连续地经受 过程A.