公开(公告)号：US09478273B2

公开(公告)日：2016-10-25

申请号：US14129506

申请日：2013-10-31

Applicant: Cyrille Dray ,  Blake C. Lin ,  Fatih Hamzaoglu ,  Liqiong Wei ,  Yih Wang

Inventor： Cyrille Dray ,  Blake C. Lin ,  Fatih Hamzaoglu ,  Liqiong Wei ,  Yih Wang

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/067 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1697

Abstract: Described is an apparatus for improving read and write margins. The apparatus comprises: a sourceline; a first bitline; a column of resistive memory cells, each resistive memory cell of the column coupled at one end to the sourceline and coupled to the first bitline at another end; and a second bitline in parallel to the first bitline, the second bitline to decouple read and write operations on the bitline for the resistive memory cell. Described is also an apparatus which comprises: a sourceline; a bitline; a column of resistive memory cells, each resistive memory cell in the column coupled at one end to the sourceline and coupled to the bitline at another end; and sourceline write drivers coupled to the bitline and the sourceline, wherein the sourceline write drivers are distributed along the column of resistive memory cells.

Abstract translation: 描述了一种用于提高读写余量的装置。 该装置包括：源线; 第一个位线 一列电阻存储器单元，该列的每个电阻存储器单元在一端耦合到源极线并且在另一端耦合到第一位线; 以及与所述第一位线并联的第二位线，所述第二位线用于解耦所述电阻存储器单元的位线上的读取和写入操作。 还描述了一种装置，其包括：源线; 有位 一列电阻存储器单元，列中的每个电阻存储器单元在一端耦合到源极线并且在另一端耦合到位线; 以及耦合到位线和源极线的源极线写入驱动器，其中源极线写入驱动器沿着电阻存储器单元的列分布。

公开(公告)号：US20140340977A1

公开(公告)日：2014-11-20

申请号：US13976403

申请日：2013-05-16

Applicant: Eric A. Karl ,  Yong-Gee Ng ,  Cyrille Dray

Inventor： Eric A. Karl ,  Yong-Gee Ng ,  Cyrille Dray

IPC: G11C5/14 ,  G11C11/419

CPC classification number: G11C11/419 ,  G11C5/147 ,  G11C11/413 ,  G11C11/414 ,  G11C11/417

Abstract: Described is an apparatus for memory write assist which consumes low power during write assist operation. The apparatus comprises: a power supply node; a device operable to adjust voltage on the power supply node; and a feedback unit coupled to the power supply node, the feedback unit to control the device in response to a voltage level of the voltage on the power supply node.

Abstract translation: 描述了一种在写入辅助操作期间消耗低功率的存储器写入辅助装置。 该装置包括：电源节点; 可操作以调节所述电源节点上的电压的装置; 以及耦合到所述电源节点的反馈单元，所述反馈单元响应于所述电源节点上的电压的电压电平来控制所述装置。

公开(公告)号：US08331166B2

公开(公告)日：2012-12-11

申请号：US13036030

申请日：2011-02-28

Applicant: Cyrille Dray ,  Alexandre Ney

Inventor： Cyrille Dray ,  Alexandre Ney

IPC: G11C5/14

CPC classification number: G11C7/02 ,  G11C7/08 ,  G11C7/14 ,  G11C2207/002

Abstract: A method and a system for reading from memory cells in a memory device are provided. In one embodiment, the memory device comprises a first plurality of data lines and a second plurality of data lines, at least one first multiplexer coupled to the first plurality of data lines and at least one low reference line, at least one second multiplexer coupled to the second plurality of data lines and at least one high reference line, at least one third multiplexer coupled to the at least one first multiplexer and the at least one second multiplexer, and a reference memory cell coupled to the at least one third multiplexer and at least one sense amplifier.

Abstract translation: 提供了一种用于从存储器件中的存储单元读取的方法和系统。 在一个实施例中，存储器设备包括第一多个数据线和第二多个数据线，耦合到第一多个数据线和至少一个低参考线的至少一个第一多路复用器，耦合到 所述第二多个数据线和至少一个高参考线，耦合到所述至少一个第一多路复用器和所述至少一个第二多路复用器的至少一个第三多路复用器，以及耦合到所述至少一个第三多路复用器的参考存储器单元， 至少一个读出放大器。

公开(公告)号：US07751229B2

公开(公告)日：2010-07-06

申请号：US11617336

申请日：2006-12-28

Applicant: Cyrille Dray ,  Francois Jacquet ,  Sébastien Barasinski

Inventor： Cyrille Dray ,  Francois Jacquet ,  Sébastien Barasinski

IPC: G11C11/00

CPC classification number: G11C11/413

Abstract: A device, and a corresponding method of implementation, for SRAM memory information storage are provided. The device is powered by a supply voltage and includes an array of base cells organized in base columns, and at least one mirror column of at least one mirror cell liable to simulate the behavior of the cells in a base column. The device further includes Emulation means, in a mirror column, of the most restricting cell in a base column, Means for varying a mirror power supply voltage (VDDMMOCK) for the mirror column, and Means for copying the mirror power supply voltage in the emulated base column.

Abstract translation: 提供了一种用于SRAM存储器信息存储的设备和相应的实现方法。 该设备由电源电压供电并且包括组合在基列中的基本单元的阵列，以及至少一个反射镜单元的至少一个反射镜列，其容易模拟基极柱中的单元的行为。 该装置还包括在立柱中的最大限制单元的反射镜中的仿真装置，用于改变反射镜列的反射镜电源电压（VDDMMOCK）的装置，以及用于将模拟的反射镜电源电压复制的装置 基列。

公开(公告)号：US20080290899A1

公开(公告)日：2008-11-27

申请号：US11805305

申请日：2007-05-23

Applicant: Cyrille Dray

Inventor： Cyrille Dray

IPC: H03K19/0175 ,  G11C8/00

CPC classification number: G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  H03K5/1534

Abstract: The invention relates to an edge transition detector, and a method of operating an edge transition detector. An integrated circuit includes an edge transition detector for producing an output signal at an output node in response to an input signal. The edge transition detector includes a switch coupled to the output node. The edge transition detector includes a logic device with a first input coupled to the input node and an output coupled to a control terminal of the switch to enable the switch to conduct, thereby effecting a transition of the output signal from a first logic level to a second logic level in response to the input signal. A feedback path is provided from the output node to a second input of the logic device to disable switch conductivity when the output signal completes the logic transition from the first logic level to the second logic level.

Abstract translation: 本发明涉及一种边缘转换检测器，以及一种操作边缘转换检测器的方法。 集成电路包括用于响应于输入信号在输出节点产生输出信号的边沿转换检测器。 边缘转换检测器包括耦合到输出节点的开关。 边缘跃迁检测器包括具有耦合到输入节点的第一输入和耦合到开关的控制端的输出的逻辑器件，以使开关能导通，从而实现输出信号从第一逻辑电平到 响应于输入信号的第二逻辑电平。 当输出信号完成从第一逻辑电平到第二逻辑电平的逻辑转换时，反馈路径从输出节点提供给逻辑器件的第二输入，以禁止开关电导率。

公开(公告)号：US07372728B2

公开(公告)日：2008-05-13

申请号：US11738987

申请日：2007-04-23

Applicant: Cyrille Dray ,  Christophe Frey ,  Jean Lasseuguette ,  Sébastien Barasinski ,  Richard Fournel

Inventor： Cyrille Dray ,  Christophe Frey ,  Jean Lasseuguette ,  Sébastien Barasinski ,  Richard Fournel

IPC: G11C11/14

CPC classification number: G11C11/15

Abstract: A random access memory array includes random access memory elements arranged in a rows and columns. The elements of each row have a word line and a write digit line and the elements of each column have a bit line and a write bit line. A first selection circuit/transistor for each row has a first source-drain path coupled in the write digit line and a gate terminal coupled to the word line. A second selection circuit/transistor for each column has a second source-drain path coupling in the write bit line and a gate terminal coupled to the bit line. A first write signal is applied to one word line to actuate the first selection circuit/transistor for the row corresponding to that one word line and cause a write current to flow through the first source-drain path of the actuated first selection circuit/transistor and the corresponding write digit line to write data into certain memory elements in that row. A second write signal is applied to one bit line to actuate the second selection circuit/transistor for the column corresponding to that one bit line and cause a write current to flow through the second source-drain path of the actuated second selection circuit/transistor and the corresponding write bit line to write data into at least one memory element in that column.

Abstract translation: 随机存取存储器阵列包括排列成行和列的随机存取存储器元件。 每行的元素具有字线和写数字线，并且每列的元素具有位线和写位线。 用于每行的第一选择电路/晶体管具有耦合在写入数字线中的第一源极 - 漏极通路和耦合到字线的栅极端子。 用于每列的第二选择电路/晶体管具有在写位线中耦合的第二源 - 漏路径和耦合到位线的栅极端。 第一写入信号被施加到一个字线以激活对应于该一条字线的行的第一选择电路/晶体管，并且使得写入电流流过被激活的第一选择电路/晶体管的第一源极 - 漏极路径，并且 相应的写数字行将数据写入该行中的某些存储器元素。 第二写入信号被施加到一个位线以启动与该一个位线相对应的列的第二选择电路/晶体管，并且使得写入电流流过被致动的第二选择电路/晶体管的第二源极 - 漏极通路，并且 相应的写位线将数据写入该列中的至少一个存储器元件。

公开(公告)号：US07110315B2

公开(公告)日：2006-09-19

申请号：US10929359

申请日：2004-08-27

Applicant: Cyrille Dray

Inventor： Cyrille Dray

IPC: G11C7/00 ,  G11C8/00

CPC classification number: G11C16/12

Abstract: A switch arrangement for switching a node between three supply voltages based on two control signals. The switch arrangement includes three circuits for connecting an output node with one of three nodes, each of which is set to a different voltage. The switch arrangement is controlled by six control signals that establish mutually exclusive switching modes and avoid combinational currents. The switch arrangement is also designed to allow the use of MOS transistors having a low nominal voltage, with a value that is lower than the highest voltage to be switched. The switch arrangement is particularly adapted to supply power to non-volatile memory cells.

Abstract translation: 一种用于基于两个控制信号在三个电源电压之间切换节点的开关装置。 开关装置包括用于将输出节点与三个节点之一连接的三个电路，每个节点被设置为不同的电压。 开关布置由六个控制信号控制，这些控制信号建立互斥开关模式并避免组合电流。 开关装置还被设计为允许使用具有低额定电压的MOS晶体管，其值低于要切换的最高电压。 开关装置特别适于向非易失性存储单元供电。

公开(公告)号：US20050219912A1

公开(公告)日：2005-10-06

申请号：US10511712

申请日：2003-01-31

Applicant: Philippe Gendrier ,  Cyrille Dray ,  Richard Fournel ,  Sebastien Poirier ,  Daniel Caspar ,  Philippe Candelier

Inventor： Philippe Gendrier ,  Cyrille Dray ,  Richard Fournel ,  Sebastien Poirier ,  Daniel Caspar ,  Philippe Candelier

IPC: H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L27/11558 ,  H01L29/66825 ,  H01L29/7881

Abstract: The semiconductor memory device includes an electrically erasable programmable non-volatile memory cell having a single layer of gate material and including a floating-gate transistor and a control gate. The source, drain and channel regions of the floating-gate transistor form the control gate. Moreover, the memory cell includes a dielectric zone lying between a first part of the layer of gate material and a first semiconductor active zone electrically isolated from a second active zone incorporating the control gate. This dielectric zone then forms a tunnel zone for transferring, during erasure of the cell, the charges stored in the floating gate to the first active zone.

Abstract translation: 半导体存储器件包括具有单层栅极材料并且包括浮栅晶体管和控制栅的电可擦除可编程非易失性存储单元。 浮栅晶体管的源极，漏极和沟道区域形成控制栅极。 此外，存储单元包括位于栅极材料层的第一部分和与结合有控制栅极的第二有源区电隔离的第一半导体有源区之间的介电区。 该介电区随后形成隧道区，用于在电池擦除期间将存储在浮动栅极中的电荷转移到第一活性区。

公开(公告)号：US06728135B2

公开(公告)日：2004-04-27

申请号：US10228164

申请日：2002-08-26

Applicant: Cyrille Dray ,  Daniel Caspar ,  Richard Fournel

Inventor： Cyrille Dray ,  Daniel Caspar ,  Richard Fournel

IPC: G11C1600

CPC classification number: H01L29/42324 ,  H01L29/7887

Abstract: The FAMOS memory location comprises a single floating gate (GR) overlapping an active surface of a semiconductor substrate according to at least two asymmetrical overlap profiles (PF1, PF2) so as to define at least two electrodes in the active region. Memory location programming means (MC, SW) are capable of selectively applying different predetermined sets of bias voltages to the electrodes so as to confer at least three programming logic levels on the memory location.

Abstract translation: FAMOS存储器位置包括根据至少两个不对称重叠轮廓（PF1，PF2）与半导体衬底的有源表面重叠的单个浮动栅极（GR），以便在有源区域中限定至少两个电极。 存储器位置编程装置（MC，SW）能够选择性地向电极施加不同的预定偏置电压组，以便在存储器位置上赋予至少三个编程逻辑电平。

公开(公告)号：US20100265758A1

公开(公告)日：2010-10-21

申请号：US12829675

申请日：2010-07-02

Applicant: Cyrille Dray ,  Francois Jacquet ,  Sébastien Barasinski

Inventor： Cyrille Dray ,  Francois Jacquet ,  Sébastien Barasinski

IPC: G11C11/00

CPC classification number: G11C11/413

Abstract: A device, and a corresponding method of implementation, for SRAM memory information storage are provided. The device is powered by a supply voltage and includes an array of base cells organized in base columns, and at least one mirror column of at least one mirror cell liable to simulate the behavior of the cells in a base column. The device further includes Emulation means, in a mirror column, of the most restricting cell in a base column, Means for varying a mirror power supply voltage for the mirror column, and Means for copying the mirror power supply voltage in the emulated base column.

Abstract translation: 提供了一种用于SRAM存储器信息存储的设备和相应的实现方法。 该设备由电源电压供电并且包括组合在基列中的基本单元的阵列，以及至少一个反射镜单元的至少一个反射镜列，其容易模拟基极柱中的单元的行为。 该装置还包括在立柱中的最大限制单元的反射镜列中的仿真装置，用于改变反射镜列的反射镜电源电压的装置和用于复制仿真基色列中的反射镜电源电压的装置。