公开(公告)号：US20150069475A1

公开(公告)日：2015-03-12

申请号：US14025041

申请日：2013-09-12

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Jean-Pierre Colinge ,  Kuo-Cheng Ching ,  Ta-Pen Guo ,  Carlos H. Diaz

IPC: H01L29/78 ,  H01L21/28

CPC classification number: H01L29/0676 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823487 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  Y10S977/762 ,  Y10S977/938

Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The channel region is separated a first distance from a first portion of the first type region. The semiconductor device includes a gate region surrounding the channel region. A first portion of the gate region is separated a second distance from the first portion of the first type region. The second distance is greater than the first distance.

Abstract translation: 半导体器件包括包括第一导电类型的第一类型区域。 半导体器件包括包括第二导电类型的第二类型区域。 半导体器件包括在第一类型区域和第二类型区域之间延伸的沟道区域。 沟道区域与第一类型区域的第一部分分开第一距离。 半导体器件包括围绕沟道区的栅极区域。 栅极区域的第一部分与第一类型区域的第一部分分开第二距离。 第二距离大于第一距离。

公开(公告)号：US12119266B2

公开(公告)日：2024-10-15

申请号：US18142142

申请日：2023-05-02

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Kuo-Cheng Ching ,  Lung-Kun Chu ,  Mao-Lin Huang ,  Chung-Wei Hsu

IPC: H01L21/82 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L21/823462 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/66795 ,  H01L29/517 ,  H01L29/518

Abstract: A method for forming a semiconductor arrangement comprises forming a first fin in a semiconductor layer. A first gate dielectric layer includes a first high-k material is formed over the first fin. A first sacrificial gate electrode is formed over the first fin. A dielectric layer is formed adjacent the first sacrificial gate electrode and over the first fin. The first sacrificial gate electrode is removed to define a first gate cavity in the dielectric layer. A second gate dielectric layer including a second dielectric material different than the first high-k material is formed over the first gate dielectric layer in the first gate cavity. A first gate electrode is formed in the first gate cavity over the second gate dielectric layer.

公开(公告)号：US11145748B2

公开(公告)日：2021-10-12

申请号：US15953920

申请日：2018-04-16

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Kuo-Cheng Ching ,  Ching-Wei Tsai ,  Chih-Hao Wang ,  Carlos H. Diaz

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/165

Abstract: One or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a channel, such as an un-doped channel, over a substrate. The semiconductor arrangement comprises a gate, such as a gate-all-around structure gate, around the channel. The semiconductor arrangement comprises an isolation structure, such as a silicon germanium oxide structure, between the gate and the substrate. The isolation structure blocks current leakage into the substrate. Because the semiconductor arrangement comprises the isolation structure, the channel can be left un-doped, which improves electron mobility and decreases gate capacitance.

公开(公告)号：US20190305097A1

公开(公告)日：2019-10-03

申请号：US16442964

申请日：2019-06-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

Inventor： Jean-Pierre COLINGE ,  Kuo-Cheng Ching ,  Ta-Pen Guo ,  Carlos H. Diaz

IPC: H01L29/417 ,  H01L29/775 ,  H01L29/66 ,  H01L21/265 ,  H01L21/266 ,  B82Y10/00 ,  H01L29/786 ,  H01L29/41 ,  H01L21/285 ,  H01L29/06 ,  B82Y40/00

Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a first silicide region on a first type surface region of the first type region. The first silicide region is separated at least one of a first distance from a first type diffusion region of the first type region or a second distance from the channel region.

公开(公告)号：US10163729B2

公开(公告)日：2018-12-25

申请号：US15924350

申请日：2018-03-19

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Kuo-Cheng Ching ,  Carlos H. Diaz ,  Jean-Pierre Colinge

IPC: H01L21/8238 ,  H01L29/423 ,  H01L29/775 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66 ,  H01L29/06 ,  H01L27/092 ,  H01L29/16 ,  H01L29/78 ,  H01L29/786

Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanowire channels and NMOS transistors comprising silicon nanowire channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanowire channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanowire channels for NMOS transistors. PMOS transistors having germanium nanowire channels and NMOS transistors having silicon nanowire channels are formed as part of a single fabrication process.

公开(公告)号：US10008566B2

公开(公告)日：2018-06-26

申请号：US14025041

申请日：2013-09-12

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Jean-Pierre Colinge ,  Kuo-Cheng Ching ,  Ta-Pen Guo ,  Carlos H. Diaz

IPC: H01L29/06 ,  H01L21/8234 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/0676 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823487 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  Y10S977/762 ,  Y10S977/938

Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The channel region is separated a first distance from a first portion of the first type region. The semiconductor device includes a gate region surrounding the channel region. A first portion of the gate region is separated a second distance from the first portion of the first type region. The second distance is greater than the first distance.

公开(公告)号：US09870949B2

公开(公告)日：2018-01-16

申请号：US15485270

申请日：2017-04-12

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Kuo-Cheng Ching ,  Guan-Lin Chen

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66818 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785

Abstract: A semiconductor device and method of formation are provided herein. A semiconductor device includes a fin having a first wall extending along a first plane, the fin including a doped region defining a first furrow on a first side of the first plane. A dielectric is disposed within the first furrow, such that the dielectric is in contact with the first furrow between a first end of the dielectric and a second end of the dielectric. The first end is separated a first distance from the first plane. The dielectric disposed within the furrow increases the isolation of a channel portion of adjacent fins, and thus decreases current leakage of a FinFet, as compared to a FinFet including fins that do not include a dielectric disposed within a furrow.

公开(公告)号：US09837537B2

公开(公告)日：2017-12-05

申请号：US14181800

申请日：2014-02-17

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Kuo-Cheng Ching ,  Guan-Lin Chen ,  Chao-Hsiung Wang ,  Chi-Wen Liu

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/417 ,  H01L27/12 ,  H01L21/84 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66795

Abstract: A semiconductor device and method of formation are provided herein. A semiconductor device includes a barrier including carbon over a fin, the fin including a doped region. The semiconductor device includes an epitaxial (Epi) cap over the barrier, the Epi cap including phosphorus. The barrier inhibits phosphorus diffusion from the Epi cap into the fin as compared to a device that lacks such a barrier. The inhibition of the phosphorus diffusion reduces a short channel effect, thus improving the semiconductor device function.

公开(公告)号：US20170236911A1

公开(公告)日：2017-08-17

申请号：US15583981

申请日：2017-05-01

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Jean-Pierre Colinge ,  Kuo-Cheng Ching ,  Ta-Pen Guo ,  Carlos H. Diaz

IPC: H01L29/417 ,  H01L21/285 ,  H01L21/266 ,  H01L29/786 ,  H01L29/06 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/41741 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/28518 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/413 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78642

Abstract: A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a channel region extending between the first type region and the second type region. The semiconductor device includes a first silicide region on a first type surface region of the first type region. The first silicide region is separated at least one of a first distance from a first type diffusion region of the first type region or a second distance from the channel region.

公开(公告)号：US20170194215A1

公开(公告)日：2017-07-06

申请号：US15463326

申请日：2017-03-20

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Kuo-Cheng Ching ,  Carlos H. Diaz ,  Jean-Pierre Colinge

IPC: H01L21/8238 ,  H01L29/78 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L21/823821 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823807 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/78 ,  H01L29/7853 ,  H01L29/78696

Abstract: Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanowire channels and NMOS transistors comprising silicon nanowire channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanowire channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanowire channels for NMOS transistors. PMOS transistors having germanium nanowire channels and NMOS transistors having silicon nanowire channels are formed as part of a single fabrication process.