公开(公告)号：US20220108956A1

公开(公告)日：2022-04-07

申请号：US17554552

申请日：2021-12-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Hao TSAI ,  Meng-Liang LIN ,  Po-Yao CHUANG ,  Techi WONG ,  Shin-Puu JENG

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L23/31 ,  H01L25/00 ,  H01L25/18 ,  H01L21/56

摘要： A method for forming a package structure is provided. The method includes forming first conductive structures and a first semiconductor die on a same side of a redistribution structure. The method includes forming an interposer substrate over the redistribution structure, wherein the first semiconductor die is between the interposer substrate and the redistribution structure, and edges of the interposer substrate extend beyond edges of the first semiconductor die. The method includes forming a second semiconductor die on the redistribution structure, wherein the first semiconductor die and the second semiconductor die are disposed on opposite sides of the redistribution structure.

公开(公告)号：US20150362526A1

公开(公告)日：2015-12-17

申请号：US14833950

申请日：2015-08-24

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Wei-Cheng WU ,  Hsien-Pin HU ,  Shang-Yun HOU ,  Shin-Puu JENG ,  Chen-Hua YU ,  Chao-Hsiang YANG

IPC分类号： G01R1/04 ,  G01R31/28 ,  G01R31/26

CPC分类号： G01R31/2896 ,  G01R1/0416 ,  G01R31/2601 ,  G01R31/2884 ,  G01R31/2886 ,  G01R31/2889 ,  G01R31/2893 ,  H01L22/32 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02377 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05147 ,  H01L2224/05552 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/0614 ,  H01L2224/0616 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/16238 ,  H01L2924/20752 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/014

摘要： A package includes a semiconductor chip. The semiconductor chip includes a test pad, and a plurality of microbump pads, wherein each microbump pad of the plurality of microbump pads is electrically connected to the test pad. The package further includes a substrate; and a plurality of microbumps configured to electrically connect the semiconductor chip to the substrate, wherein each microbump of the plurality of microbumps is electrically connected to a corresponding microbump pad of the plurality of microbump pads. The package further includes a package substrate, wherein the package substrate comprises a bump pad, wherein an area of the bump pad is greater than a combined area of the test pad and the plurality of microbump pads. The package further includes a bump configured to electrically connect the substrate to the package substrate.

摘要翻译： 封装包括半导体芯片。 半导体芯片包括测试焊盘和多个微型块焊盘，其中多个微型块焊盘中的每个微型焊盘电连接到测试焊盘。 所述封装还包括衬底; 以及多个微胶片，其被配置为将所述半导体芯片电连接到所述基板，其中所述多个微胶片中的每个微小块电连接到所述多个微型块衬垫中的对应的微型块体。 封装还包括封装衬底，其中封装衬底包括凸块焊盘，其中凸块焊盘的面积大于测试焊盘和多个微型块焊盘的组合面积。 所述封装还包括凸起，所述凸起被配置为将所述衬底电连接到所述封装衬底。

公开(公告)号：US20140014959A1

公开(公告)日：2014-01-16

申请号：US14028673

申请日：2013-09-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shin-Puu JENG ,  Wei-Cheng WU ,  Shang-Yun HOU ,  Chen-Hua YU ,  Tzuan-Horng LIU ,  Tzu-Wei CHIU ,  Kuo-Ching HSU

IPC分类号： H01L21/66 ,  H01L21/768

CPC分类号： H01L22/34 ,  G01R31/2884 ,  H01L21/76885 ,  H01L22/32 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/02126 ,  H01L2224/0401 ,  H01L2224/05001 ,  H01L2224/0554 ,  H01L2224/10126 ,  H01L2224/13005 ,  H01L2224/16225 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/00

摘要： A packaged IC chip includes a testing pad, wherein the testing pad is electrically connected to devices in the packaged integrated circuit chip. The packaged IC chip further includes a first passivation layer over a portion of the testing pad, and a second passivation layer covering a surface of the testing pad and a portion of the first passivation layer surrounding the testing region of the testing pad. A distance between edges of the second passivation layer covering the surface of the testing pad to edges of the testing pad is in a range from about 2 mm to about 15 mm.

摘要翻译： 封装的IC芯片包括测试焊盘，其中测试焊盘与封装的集成电路芯片中的器件电连接。 封装的IC芯片还包括在测试焊盘的一部分上的第一钝化层，以及覆盖测试焊盘的表面的第二钝化层和围绕测试焊盘的测试区域的第一钝化层的一部分。 覆盖测试垫表面的第二钝化层的边缘与测试垫边缘之间的距离在约2mm至约15mm的范围内。

公开(公告)号：US20240334608A1

公开(公告)日：2024-10-03

申请号：US18740889

申请日：2024-06-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Kuei HSU ,  Ming-Chih YEW ,  Po-Chen LAI ,  Po-Yao LIN ,  Shin-Puu JENG

IPC分类号： H05K1/18 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H05K3/28 ,  H05K3/34

CPC分类号： H05K1/181 ,  H01L25/0655 ,  H05K3/284 ,  H01L23/3185 ,  H01L23/49811 ,  H01L23/5383 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/95001 ,  H05K3/3436 ,  H05K2201/10378 ,  H05K2201/10727 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2203/107

摘要： A method for forming a semiconductor package is provided. The method includes mounting a semiconductor device on a surface of a package substrate. The method also includes forming an underfill element between the semiconductor device and the surface of the package substrate. The underfill element includes a fillet portion that extends laterally beyond the periphery of the semiconductor device and is formed along the periphery of the semiconductor device. The method also includes forming one or more grooves in the fillet portion.

公开(公告)号：US20240153839A1

公开(公告)日：2024-05-09

申请号：US18411392

申请日：2024-01-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shu-Shen YEH ,  Po-Yao LIN ,  Chin-Hua WANG ,  Yu-Sheng LIN ,  Shin-Puu JENG

IPC分类号： H01L23/367 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L23/3675 ,  H01L21/4857 ,  H01L21/4882 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0655 ,  H01L2224/16235 ,  H01L2224/29017 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/1815 ,  H01L2924/182 ,  H01L2924/3511 ,  H01L2924/35121

摘要： A semiconductor package structure includes an interposer substrate formed over a package substrate. The structure also includes a die disposed over the interposer substrate. The structure also includes a first heat spreader disposed over the package substrate. The structure also includes a second heat spreader disposed over the die and connected to the first heat spreader. The coefficient of thermal expansion (CTE) of the first heat spreader and the coefficient of thermal expansion of the second heat spreader are different.

公开(公告)号：US20240120294A1

公开(公告)日：2024-04-11

申请号：US18391891

申请日：2023-12-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shu-Shen YEH ,  Chin-Hua WANG ,  Kuang-Chun LEE ,  Po-Yao LIN ,  Shyue-Ter LEU ,  Shin-Puu JENG

IPC分类号： H01L23/00 ,  H01L23/04 ,  H01L23/10 ,  H01L23/367

CPC分类号： H01L23/562 ,  H01L23/04 ,  H01L23/10 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/49816

摘要： A chip package includes a substrate, a semiconductor chip, and a thermal conductive structure. The chip package includes a first and a second support structures below the thermal conductive structure. The first and the second support structures connect the substrate and corners of the thermal conductive structure. The thermal conductive structure has a side edge connecting the first and the second support structures. The first and the second support structures and the side edge together define of an opening exposing a space surrounding the semiconductor chip. The first and the second support structures are disposed along a side of the substrate. The first support structure is laterally separated from the side of the substrate by a first lateral distance. The side edge of the thermal conductive structure is laterally separated from the side of the substrate by a second lateral distance different than the first lateral distance.

公开(公告)号：US20240096822A1

公开(公告)日：2024-03-21

申请号：US18520971

申请日：2023-11-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chia-Kuei HSU ,  Ming-Chih YEW ,  Shu-Shen YEH ,  Che-Chia YANG ,  Po-Yao LIN ,  Shin-Puu JENG

IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065

CPC分类号： H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0655 ,  H01L2221/68372 ,  H01L2224/16227 ,  H01L2924/18161 ,  H01L2924/3512

摘要： A package structure is provided. The package structure includes a first conductive pad in a first insulating layer, a conductive via in a second insulating layer directly under the first conductive pad, and a first under bump metallurgy structure directly under the first conductive via. In a first horizontal direction, the conductive via is narrower than the first under bump metallurgy structure, and the first under bump metallurgy structure is narrower than the first conductive pad.

公开(公告)号：US20230395520A1

公开(公告)日：2023-12-07

申请号：US17833820

申请日：2022-06-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Li-Ling LIAO ,  Ming-Chih YEW ,  Chia-Kuei HSU ,  Shin-Puu JENG

IPC分类号： H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

CPC分类号： H01L23/5389 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/20 ,  H01L24/19 ,  H01L2924/35121 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L2221/68359 ,  H01L2224/214 ,  H01L21/6835

摘要： A package structure includes an interposer, a die, a conductive terminal and an interconnection structure that is disposed on a first side of the interposer. The die is electrically bonded to the interposer and disposed over the interconnection structure. The conductive terminal is connected to the interposer and the die via a conductive bump. In order to effectively avoid cold joint issues, round or rectangular polyimide structures are first disposed under the bumps to structurally support the bump and sufficiently increase bump height for improved electrical connection and long term reliability of the package structure.

公开(公告)号：US20230378076A1

公开(公告)日：2023-11-23

申请号：US18358714

申请日：2023-07-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shin-Puu JENG ,  Shuo-Mao CHEN ,  Feng-Cheng HSU ,  Po-Yao LIN

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L21/78 ,  H01L23/31 ,  H01L25/16

CPC分类号： H01L23/5385 ,  H01L24/81 ,  H01L21/568 ,  H01L21/4853 ,  H01L21/78 ,  H01L21/561 ,  H01L23/5383 ,  H01L24/16 ,  H01L23/3128 ,  H01L23/562 ,  H01L25/162 ,  H01L21/4857 ,  H01L24/13 ,  H01L2224/16227 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144

摘要： A chip package structure is provided. The chip package structure includes a first redistribution structure having a first surface and a second surface. The first redistribution structure includes a first pad and a second pad, the first pad is adjacent to the first surface, and the second pad is adjacent to and exposed from the second surface. The chip package structure includes a chip package bonded to the first pad through a first bump, wherein a first width of the first pad decreases in a first direction away from the chip package, and a second width of the second pad decreases in the first direction. The chip package structure includes a second bump over the second pad.

公开(公告)号：US20230326879A1

公开(公告)日：2023-10-12

申请号：US18328913

申请日：2023-06-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Chen LAI ,  Chin-Hua WANG ,  Ming-Chih YEW ,  Li-Ling LIAO ,  Tsung-Yen LEE ,  Po-Yao LIN ,  Shin-Puu JENG

IPC分类号： H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L23/16

CPC分类号： H01L23/562 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/08 ,  H01L21/6835 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L23/16 ,  H01L2221/68372 ,  H01L2224/16227 ,  H01L2924/18161 ,  H01L2924/3512

摘要： A package structure is provided. The package structure includes a semiconductor die bonding on a first surface of a redistribution structure through first bonding elements, and a wall structure bonding on the first surface of the redistribution structure through second bonding elements. The wall structure includes a plurality of partitions laterally arranged in a discontinuous ring, and the semiconductor die is located within the discontinuous ring. The package structure also includes a substrate on a second surface of the redistribution structure through third bonding elements and in electrical connection with the semiconductor die