公开(公告)号：US20180151565A1

公开(公告)日：2018-05-31

申请号：US15602807

申请日：2017-05-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tung Ying LEE ,  Ziwei FANG ,  Yee-Chia YEO ,  Meng-Hsuan HSIAO

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/08 ,  H01L21/768 ,  H01L21/02 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L27/0886 ,  H01L21/02532 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848

Abstract: In a method of forming a FinFET, a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is recessed so that a remaining layer of the first sacrificial layer is formed on the isolation insulating layer and an upper portion of the source/drain structure is exposed. A second sacrificial layer is formed on the remaining layer and the exposed source/drain structure. The second sacrificial layer and the remaining layer are patterned, thereby forming an opening. A dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first and second sacrificial layers are removed to form a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.

公开(公告)号：US20160225906A1

公开(公告)日：2016-08-04

申请号：US14613663

申请日：2015-02-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Tsan-Chun WANG ,  Ziwei FANG ,  Chien-Tai CHAN ,  Da-Wen LIN ,  Huicheng CHANG

IPC: H01L29/78 ,  H01L21/266 ,  H01L21/324 ,  H01L29/66

CPC classification number: H01L29/7856 ,  H01L21/2253 ,  H01L21/266 ,  H01L21/324 ,  H01L29/66795

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a doped region in an upper portion of the substrate. The doped region is doped with first dopants of a first conduction type. The semiconductor device structure includes one fin structure over the substrate. A first dopant concentration of the doped region exposed by the fin structure is greater than a second dopant concentration of the doped region covered by the fin structure. The semiconductor device structure includes an isolation layer over the substrate and at two opposite sides of the fin structure. The semiconductor device structure includes a gate over the isolation layer and the fin structure.

Abstract translation: 提供半导体器件结构。 半导体器件结构包括在衬底的上部具有掺杂区的衬底。 掺杂区域掺杂有第一导电类型的第一掺杂剂。 半导体器件结构包括在衬底上的一个鳍结构。 通过鳍结构暴露的掺杂区域的第一掺杂剂浓度大于由鳍结构覆盖的掺杂区域的第二掺杂剂浓度。 半导体器件结构包括在衬底上并在鳍结构的两个相对侧的隔离层。 半导体器件结构包括隔离层上的栅极和鳍结构。

公开(公告)号：US20240186414A1

公开(公告)日：2024-06-06

申请号：US18402455

申请日：2024-01-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming LIN ,  Sai-Hooi YEONG ,  Ziwei FANG ,  Bo-Feng YOUNG ,  Chi On CHUI ,  Chih-Yu CHANG ,  Huang-Lin CHAO

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/78391 ,  H01L21/02181 ,  H01L21/0234 ,  H01L21/02356 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/66795 ,  H01L29/6684 ,  H01L29/7851

Abstract: The present disclosure relates to a semiconductor device includes a substrate and first and second spacers on the substrate. The semiconductor device includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers. The first portion includes a crystalline material and the second portion comprises an amorphous material. The gate stack further includes a gate electrode on the first and second portions of the gate dielectric layer.

公开(公告)号：US20230377993A1

公开(公告)日：2023-11-23

申请号：US18227744

申请日：2023-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG ,  Ziwei FANG

IPC: H01L21/8238 ,  H01L29/423 ,  H01L29/49 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/285 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L27/092

CPC classification number: H01L21/823842 ,  H01L29/42392 ,  H01L29/4966 ,  H01L21/28088 ,  H01L21/823807 ,  H01L21/32139 ,  H01L21/32133 ,  H01L21/28556 ,  H01L21/823821 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/0847 ,  H01L27/0924

Abstract: The structure of a semiconductor device with different gate structures configured to provide ultra-low threshold voltages and a method of fabricating the semiconductor device are disclosed. The semiconductor device includes first and second nanostructured channel regions in first and second nanostructured layers, respectively, and first and second gate-all-around (GAA) structures surrounding the first and second nanostructured channel regions, respectively. The first GAA structure includes an Al-based gate stack with a first gate dielectric layer, an Al-based n-type work function metal layer, a first metal capping layer, and a first gate metal fill layer. The second GAA structure includes an Al-free gate stack with a second gate dielectric layer, an Al-free p-type work function metal layer, a metal growth inhibition layer, a second metal capping layer, and a second gate metal fill layer.

公开(公告)号：US20210098589A1

公开(公告)日：2021-04-01

申请号：US16589957

申请日：2019-10-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG ,  Ziwei FANG

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/51 ,  H01L29/49 ,  H01L21/8234

Abstract: A method for forming a semiconductor structure is provided. The method for forming the semiconductor structure includes alternately stacking first semiconductor layers and second semiconductor layers over a substrate, patterning the first semiconductor layers and the second semiconductor layers into a fin structure, removing the first semiconductor layers of the fin structure thereby forming gaps between the second semiconductor layers of the fin structure, forming a gate dielectric layer wrapping around the second semiconductor layers, forming a barrier material on the gate dielectric layer. At least a portion of the barrier material is oxidized to form a first barrier oxide. The method for forming the semiconductor structure also includes etching away the first barrier oxide, forming a work function layer to wrap around the second semiconductor layers, and forming a metal fill layer over the work function layer.

公开(公告)号：US20200303259A1

公开(公告)日：2020-09-24

申请号：US16897229

申请日：2020-06-09

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yasutoshi OKUNO ,  Cheng-Yi PENG ,  Ziwei FANG ,  I-Ming CHANG ,  Akira MINEJI ,  Yu-Ming LIN ,  Meng-Hsuan HSIAO

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/203 ,  H01L27/092 ,  H01L21/8238

Abstract: A method of forming a semiconductor device including a fin field effect transistor (FinFET), the method includes forming a first sacrificial layer over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of the opening and on at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, forming a dielectric layer in the opening. After the dielectric layer is formed, removing the patterned first sacrificial layer, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening. The FinFET is an n-type FET, and the source/drain structure includes an epitaxial layer made of Si1-y-a-bGeaSnbM2y, wherein 0

公开(公告)号：US20200294865A1

公开(公告)日：2020-09-17

申请号：US16353493

申请日：2019-03-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG ,  Ziwei FANG

IPC: H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L29/49 ,  H01L29/06 ,  H01L21/28 ,  H01L27/092 ,  H01L21/02 ,  H01L21/306 ,  H01L21/033

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a work function material around a first semiconductor layer in a first region and a second semiconductor layer in a second region. The method also includes forming a first gate electrode material over the work function material. The method also includes removing the first gate electrode material in the first region. The method also includes forming a second gate electrode material over the work function material in the first region.

公开(公告)号：US20200243522A1

公开(公告)日：2020-07-30

申请号：US16258004

申请日：2019-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang CHENG ,  Ziwei FANG

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L21/8238 ,  H01L21/28 ,  H01L21/308 ,  H01L21/02

Abstract: A method of fabricating semiconductor devices is provided. The method includes forming a fin structure including a stack of alternating first and second semiconductor layers on a substrate, removing the first semiconductor layers to form spaces between the second semiconductor layers, and depositing a gate dielectric layer to surround the second semiconductor layers. The method also includes depositing a first oxygen blocking layer and removing the native oxide thereof, depositing an n-type work function layer, and forming a second oxygen blocking layer in sequence on the gate dielectric layer to surround the second semiconductor layers in the same process chamber. The second oxygen blocking layer includes a capping layer and a capping film. The method further includes forming a metal gate fill material over the capping film to form a gate-all-around structure.

公开(公告)号：US20190067083A1

公开(公告)日：2019-02-28

申请号：US16173492

申请日：2018-10-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： De-Wei YU ,  Tsu-Hsiu PERNG ,  Ziwei FANG

IPC: H01L21/762 ,  H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/02

CPC classification number: H01L21/76224 ,  H01L21/02354 ,  H01L21/28518 ,  H01L21/768 ,  H01L21/76825 ,  H01L21/76828 ,  H01L21/76897 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method of semiconductor device fabrication includes providing a substrate having a hardmask layer thereover. The hardmask layer is patterned to expose the substrate. The substrate is etched through the patterned hardmask layer to form a first fin element and a second fin element extending from the substrate. An isolation feature between the first and second fin elements is formed, where the isolation feature has a first etch rate in a first solution. A laser anneal process is performed to irradiate the isolation feature with a pulsed laser beam. A pulse duration of the pulsed laser beam is adjusted based on a height of the isolation feature. The isolation feature after performing the laser anneal process has a second etch rate less than the first etch rate in the first solution.

公开(公告)号：US20180263684A1

公开(公告)日：2018-09-20

申请号：US15988624

申请日：2018-05-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tung Ying LEE ,  Ziwei FANG ,  Yee-Chia YEO ,  Meng-Hsuan HSIAO

IPC: A61B18/14 ,  A61B18/00

CPC classification number: A61B18/1445 ,  A61B17/285 ,  A61B17/29 ,  A61B17/295 ,  A61B2017/2825 ,  A61B2017/2926 ,  A61B2018/00184 ,  A61B2018/00589 ,  A61B2018/00601 ,  A61B2018/0063 ,  A61B2018/1455 ,  A61B2018/1465 ,  A61B2090/034

Abstract: In a method of forming a FinFET, a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is recessed so that a remaining layer of the first sacrificial layer is formed on the isolation insulating layer and an upper portion of the source/drain structure is exposed. A second sacrificial layer is formed on the remaining layer and the exposed source/drain structure. The second sacrificial layer and the remaining layer are patterned, thereby forming an opening. A dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first and second sacrificial layers are removed to form a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.