公开(公告)号：US20180019207A1

公开(公告)日：2018-01-18

申请号：US15714172

申请日：2017-09-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Wei Peng ,  Chih-Ming Lai ,  Chun-Kuang Chen ,  Chih-Liang Chen ,  Charles Chew-Yuen Young ,  Jiann-Tyng Tzeng ,  Kam-Tou Sio ,  Ru-Gun Liu ,  Yung-Sung Yen

IPC分类号： H01L23/528 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L23/5286 ,  H01L21/76816 ,  H01L21/76892 ,  H01L23/5226 ,  H01L23/528 ,  H01L28/00

摘要： In some embodiments, the present disclosure relates to an integrated chip having a lower power rail continuously extending over a plurality of gate structures. A first set of connection pins straddle a first edge of the lower power rail, and a second set of connection pins straddle a second edge of the lower power rail, which is opposite the first edge. The first set of connection pins and the second set of connection pins are electrically coupled to the lower power rail. An upper power rail is over the lower power rail and is electrically coupled to the first set of connection pins and the second set of connection pins. The first set of connection pins are arranged at a first pitch and the second set of connection pins arranged with respect to the first set of connection pins at a second pitch less than the first pitch.

公开(公告)号：US11923297B2

公开(公告)日：2024-03-05

申请号：US17242056

申请日：2021-04-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-An Lai ,  Shih-Wei Peng ,  Wei-Cheng Lin ,  Jiann-Tyng Tzeng

IPC分类号： H01L23/528 ,  G06F30/394 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  G06F30/31 ,  G06F30/398

CPC分类号： H01L23/528 ,  G06F30/394 ,  H01L21/0259 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/0922 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696 ,  G06F30/31 ,  G06F30/398

摘要： Apparatus and methods for generating a physical layout for a high density routing circuit are disclosed. An exemplary semiconductor structure includes: a gate structure; a plurality of first metal lines formed in a first dielectric layer below the gate structure; at least one first via formed in a second dielectric layer between the gate structure and the first dielectric layer; a plurality of second metal lines formed in a third dielectric layer over the gate structure; and at least one second via formed in a fourth dielectric layer between the gate structure and the third dielectric layer. Each of the at least one first via is electrically connected to the gate structure and a corresponding one of the plurality of first metal lines. Each of the at least one second via is electrically connected to the gate structure and a corresponding one of the plurality of second metal lines.

公开(公告)号：US11916074B2

公开(公告)日：2024-02-27

申请号：US17875060

申请日：2022-07-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Wei Peng ,  Hui-Zhong Zhuang ,  Jiann-Tyng Tzeng ,  Li-Chun Tien ,  Pin-Dai Sue ,  Wei-Cheng Lin

IPC分类号： H01L21/70 ,  H01L27/092 ,  H03K17/687

CPC分类号： H01L27/092 ,  H03K17/6872

摘要： Exemplary embodiments for an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor. These exemplary integrated circuit layouts disclose various configurations and arrangements of various geometric shapes that are situated within an oxide diffusion (OD) layer, a polysilicon layer, a metal diffusion (MD) layer, the first metal layer, and/or a second metal layer of a semiconductor stack. In the exemplary embodiments to follow, the various geometric shapes within the first metal layer are situated within the multiple rows of the electronic device design real estate and the various geometric shapes within the OD layer, the polysilicon layer, the MD layer, and/or the second metal layer are situated within multiple columns of the electronic device design real estate.

公开(公告)号：US11817392B2

公开(公告)日：2023-11-14

申请号：US17035160

申请日：2020-09-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Shih-Wei Peng ,  Chia-Tien Wu ,  Jiann-Tyng Tzeng

IPC分类号： H01L23/538 ,  H01L21/768

CPC分类号： H01L23/5384 ,  H01L21/76802 ,  H01L21/76879 ,  H01L23/5386

摘要： An integrated circuit is disclosed. The integrated circuit includes conductive rails, signal rails, at least one first via, and at least one first conductive segment. The at least one first via is disposed between the first conductive layer and the second conductive layer, and couples a first signal rail of the signal rails to at least one of the conductive rails. The first signal rail is configured to transmit a supply signal through the at least one first via and the at least one of the conductive rails to at least one element of the integrated circuit. The at least one first conductive segment is disposed between the first conductive layer and the second conductive layer. The at least one first conductive segment is coupled to the at least one of the conductive rails and is separate from the first signal rail.

公开(公告)号：US11532751B2

公开(公告)日：2022-12-20

申请号：US17068444

申请日：2020-10-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Liang Chen ,  Charles Chew-Yuen Young ,  Hui-Ting Yang ,  Jiann-Tyng Tzeng ,  Kam-Tou Sio ,  Shih-Wei Peng ,  Wei-Cheng Lin ,  Lei-Chun Chou

IPC分类号： H01L29/78 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/48 ,  H01L27/088 ,  H01L29/66 ,  H01L29/417 ,  H01L21/74 ,  H01L23/538 ,  H01L21/3213 ,  H01L23/528 ,  H01L23/535

摘要： The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices. This isolation prevents electrical connection between the one or more metal rail conductors and the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

公开(公告)号：US20220344255A1

公开(公告)日：2022-10-27

申请号：US17242056

申请日：2021-04-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei-An Lai ,  Shih-Wei Peng ,  Wei-Cheng Lin ,  Jiann-Tyng Tzeng

IPC分类号： H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66 ,  G06F30/394

摘要： Apparatus and methods for generating a physical layout for a high density routing circuit are disclosed. An exemplary semiconductor structure includes: a gate structure; a plurality of first metal lines formed in a first dielectric layer below the gate structure; at least one first via formed in a second dielectric layer between the gate structure and the first dielectric layer; a plurality of second metal lines formed in a third dielectric layer over the gate structure; and at least one second via formed in a fourth dielectric layer between the gate structure and the third dielectric layer. Each of the at least one first via is electrically connected to the gate structure and a corresponding one of the plurality of first metal lines. Each of the at least one second via is electrically connected to the gate structure and a corresponding one of the plurality of second metal lines.

公开(公告)号：US11476250B2

公开(公告)日：2022-10-18

申请号：US17120839

申请日：2020-12-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Wei Peng ,  Hui-Zhong Zhuang ,  Jiann-Tyng Tzeng ,  Li-Chun Tien ,  Pin-Dai Sue ,  Wei-Cheng Lin

IPC分类号： H01L21/70 ,  H01L27/092 ,  H03K17/687

摘要： Exemplary embodiments for an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor. These exemplary integrated circuit layouts disclose various configurations and arrangements of various geometric shapes that are situated within an oxide diffusion (OD) layer, a polysilicon layer, a metal diffusion (MD) layer, the first metal layer, and/or a second metal layer of a semiconductor stack. In the exemplary embodiments to follow, the various geometric shapes within the first metal layer are situated within the multiple rows of the electronic device design real estate and the various geometric shapes within the OD layer, the polysilicon layer, the MD layer, and/or the second metal layer are situated within multiple columns of the electronic device design real estate.

公开(公告)号：US20210375761A1

公开(公告)日：2021-12-02

申请号：US17126509

申请日：2020-12-18

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shang-Wen Chang ,  Yi-Hsun Chiu ,  Cheng-Chi Chuang ,  Ching-Wei Tsai ,  Wei-Cheng Lin ,  Shih-Wei Peng ,  Jiann-Tyng Tzeng

IPC分类号： H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66 ,  H01L23/00

摘要： In an embodiment, a method of forming a structure includes forming a first transistor and a second transistor over a first substrate; forming a front-side interconnect structure over the first transistor and the second transistor; etching at least a backside of the first substrate to expose the first transistor and the second transistor; forming a first backside via electrically connected to the first transistor; forming a second backside via electrically connected to the second transistor; depositing a dielectric layer over the first backside via and the second backside via; forming a first conductive line in the dielectric layer, the first conductive line being a power rail electrically connected to the first transistor through the first backside via; and forming a second conductive line in the dielectric layer, the second conductive line being a signal line electrically connected to the second transistor through the second backside via.

公开(公告)号：US11080454B2

公开(公告)日：2021-08-03

申请号：US16850849

申请日：2020-04-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Shih-Wei Peng ,  Chih-Ming Lai ,  Jiann-Tyng Tzeng

IPC分类号： G06F30/392 ,  H01L23/538

摘要： A method of generating an integrated circuit (IC) layout diagram includes arranging first conductive feature layout patterns in a cell region. The first conductive feature layout patterns extend in a first direction, and the cell region has opposite first and second cell boundaries extending in a second direction. Second conductive feature layout patterns are arranged in the cell region and extending in the first direction. The first and second conductive feature layout patterns are alternately arranged. First cut feature layout patterns are arranged on the first cell boundary of the cell region and on ends of the first conductive feature layout patterns. One of the first cut feature layout patterns is offset from another one of the first cut feature layout patterns in the first direction. The IC layout diagram including the first and second conductive feature layout patterns and the first cut feature layout patterns is generated.

公开(公告)号：US12094777B2

公开(公告)日：2024-09-17

申请号：US17730801

申请日：2022-04-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Shih-Wei Peng ,  Wei-Cheng Lin ,  Jiann-Tyng Tzeng

IPC分类号： H01L21/8234 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/823412 ,  H01L29/1079 ,  H01L29/66537 ,  H01L29/7836

摘要： A method includes forming a first transistor and a second transistor over a substrate, wherein the first transistor comprises a first source/drain, a second source/drain, and a first gate between the first and second source/drains, and the second transistor comprises a third source/drain, a fourth source/drain, and a second gate between the third and fourth source/drains; forming an isolation layer to cover the second source/drain of the first transistor; and forming a first source/drain contact on and in contact the fourth source/drain of the second transistor and the isolation layer.