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    EMBEDDED MEMORY DEVICE BETWEEN NONCONTIGOUS INTERCONNECT METAL LAYERS
    21.
    发明申请
    EMBEDDED MEMORY DEVICE BETWEEN NONCONTIGOUS INTERCONNECT METAL LAYERS 有权

    公开(公告)号：US20180040817A1

    公开(公告)日：2018-02-08

    申请号：US15230690

    申请日：2016-08-08

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Harry-Hak-Lay Chuang ,  Chun-Heng Liao

    IPC: H01L45/00 ,  H01L27/22

    CPC classification number: H01L45/1233 ,  H01L27/222 ,  H01L27/228 ,  H01L27/2436 ,  H01L43/08 ,  H01L43/12 ,  H01L45/04 ,  H01L45/146

    Abstract: The present disclosure relates an integrated circuit (IC). The IC comprises a memory region and a logic region. A lower metal layer is disposed over a substrate, and comprises a first lower metal line within the memory region. An upper metal layer overlies the lower metal layer, and comprises a first upper metal line within the memory region. A memory cell is disposed between the first lower metal line and the first upper metal line, and comprises a planar bottom electrode. The planar bottom electrode abuts a first lower metal via of the lower metal layer. By forming the planar bottom electrode and connecting the planar bottom electrode to the lower metal layer through the lower metal via, no additional BEVA planarization and/or patterning processes are needed. As a result, risk of damaging the lower metal lines are reduced, thereby providing more reliable read/write operations and/or better performance.

    METHOD FOR MANUFACTURING A FINGER TRENCH CAPACITOR WITH A SPLIT-GATE FLASH MEMORY CELL
    26.
    发明申请
    METHOD FOR MANUFACTURING A FINGER TRENCH CAPACITOR WITH A SPLIT-GATE FLASH MEMORY CELL 有权
    用分离器闪存存储器单元制造指状电容电容器的方法

    公开(公告)号：US20160379988A1

    公开(公告)日：2016-12-29

    申请号：US14750071

    申请日：2015-06-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Harry-Hak-Lay Chuang ,  Yu-Hsiung Wang ,  Chen-Chin Liu

    IPC: H01L27/115

    CPC classification number: H01L27/11575 ,  H01L27/0629 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/945

    Abstract: A method for forming a split-gate flash memory cell, and the resulting integrated circuit, are provided. A semiconductor substrate having memory cell and capacitor regions are provided. The capacitor region includes one or more sacrificial shallow trench isolation (STI) regions. A first etch is performed into the one or more sacrificial STI regions to remove the one or more sacrificial STI regions and to expose one or more trenches corresponding to the one or more sacrificial STI regions. Dopants are implanted into regions of the semiconductor substrate lining the one or more trenches. A conductive layer is formed filling the one or more trenches. A second etch is performed into the conductive layer to form one of a control gate and a select gate of a memory cell over the memory cell region, and to form an upper electrode of a finger trench capacitor over the capacitor region.

    Abstract translation: 提供了一种用于形成分裂栅极闪存单元的方法，以及所得到的集成电路。 提供了具有存储单元和电容器区域的半导体衬底。 电容器区域包括一个或多个牺牲浅沟槽隔离（STI）区域。 执行第一蚀刻到一个或多个牺牲STI区域中以去除一个或多个牺牲STI区域并暴露对应于一个或多个牺牲STI区域的一个或多个沟槽。 将掺杂剂注入衬在一个或多个沟槽上的半导体衬底的区域中。 形成填充一个或多个沟槽的导电层。 执行第二蚀刻到导电层中以在存储单元区域上形成存储单元的控制栅极和选择栅极之一，并且在电容器区域上形成手指沟槽电容器的上部电极。

    Dummy bottom electrode in interconnect to reduce CMP dishing
    27.
    发明授权
    Dummy bottom electrode in interconnect to reduce CMP dishing 有权
    互连中的虚拟底部电极，以减少CMP凹陷

    公开(公告)号：US09502466B1

    公开(公告)日：2016-11-22

    申请号：US14810763

    申请日：2015-07-28

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Harry-Hak-Lay Chuang ,  Wen-Chun You

    IPC: H01L27/00 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

    CPC classification number: H01L27/2436 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/222 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1608

    Abstract: The present disclosure relates an integrated circuit (IC). The IC comprises a plurality of lower metal lines disposed within a lower inter-layer dielectric (ILD) layer over the substrate. The IC further comprises a plurality of memory cells disposed over the ILD layer and the lower metal lines at a memory region, a memory cell comprising a top electrode and a bottom electrode separated by a resistance switching element. The IC further comprises a dummy structure arranged directly above a first lower metal line at a logic region adjacent to the memory region, comprising a dummy bottom electrode and a dielectric mask on the dummy bottom electrode. The IC further comprises a top etch stop layer disposed on a bottom etch stop layer and extending upwardly along sidewalls of the dummy structure and overlying an upper surface of the dummy structure.

    Abstract translation: 本发明涉及集成电路（IC）。 IC包括设置在衬底上的下层间电介质（ILD）层内的多个下金属线。 IC还包括设置在ILD层上的多个存储单元和存储区域中的下金属线，存储单元包括由电阻切换元件分离的顶电极和底电极。 IC还包括在与存储区域相邻的逻辑区域正下方布置的虚拟结构，在虚拟底部电极上包括虚拟底部电极和电介质掩模。 IC还包括顶部蚀刻停止层，其设置在底部蚀刻停止层上并沿虚拟结构的侧壁向上延伸并且覆盖在虚拟结构的上表面上。

    SILICON RECESS ETCH AND EPITAXIAL DEPOSIT FOR SHALLOW TRENCH ISOLATION (STI)
    28.
    发明申请
    SILICON RECESS ETCH AND EPITAXIAL DEPOSIT FOR SHALLOW TRENCH ISOLATION (STI) 有权
    硅胶分离和外延沉积用于低温分离（STI）

    公开(公告)号：US20150364575A1

    公开(公告)日：2015-12-17

    申请号：US14835958

    申请日：2015-08-26

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Wei Cheng Wu ,  Kong-Pin Chang ,  Chia Ming Liang ,  Meng-Fang Hsu ,  Ching-Feng Fu ,  Shih-Ting Hung

    IPC: H01L29/66 ,  H01L21/762 ,  H01L21/8234

    CPC classification number: H01L29/0649 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66651 ,  H01L29/7833 ,  H01L29/7851

    Abstract: Some embodiments of the present disclosure relate to a method. In this method, a semiconductor substrate, which has an active region disposed in the semiconductor substrate, is received. A shallow trench isolation (STI) structure is formed to laterally surround the active region. An upper surface of the active region bounded by the STI structure is recessed to below an upper surface of the STI structure. The recessed upper surface extends continuously between inner sidewalls of the STI structure and leaves upper portions of the inner sidewalls of the STI structure exposed. A semiconductor layer is epitaxially grown on the recessed surface of the active region between the inner sidewalls of the STI structure. A gate dielectric is formed over the epitaxially-grown semiconductor layer. A conductive gate electrode is formed over the gate dielectric.

    Abstract translation: 本公开的一些实施例涉及一种方法。 在该方法中，接收具有设置在半导体衬底中的有源区的半导体衬底。 形成浅沟槽隔离（STI）结构以横向围绕有源区域。 由STI结构限定的有源区的上表面凹入到STI结构的上表面的下方。 凹陷的上表面在STI结构的内侧壁之间连续延伸，并且使STI结构的内侧壁的上部露出。 在STI结构的内侧壁之间的有源区的凹面上外延生长半导体层。 在外延生长的半导体层上形成栅极电介质。 在栅极电介质上形成导电栅电极。

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