公开(公告)号：US11101212B2

公开(公告)日：2021-08-24

申请号：US16423723

申请日：2019-05-28

Applicant: Texas Instruments Incorporated

Inventor： Dhishan Kande ,  Qi-Zhong Hong ,  Abbas Ali ,  Gregory B. Shinn

IPC: H01L23/522 ,  H01L21/768 ,  H01L49/02 ,  H01L23/532

Abstract: A device including a thin film resistor (TFR) structure. The TFR structure is accessible by one or more conductive vias that extend vertically from an upper metal layer to completely penetrate a TFR layer positioned thereunder. The conductive vias are coupled to one or more sidewalls of the TFR layer at or near the sites of penetration. The TFR structure can be manufactured by a method that includes etching a via trench completely through the TFR layer and a dielectric layer above the TFR layer, and filling the via trench with a conductor coupled to a sidewall of the TFR layer.

公开(公告)号：US10361095B2

公开(公告)日：2019-07-23

申请号：US15981725

申请日：2018-05-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abbas Ali ,  Dhishan Kande ,  Qi-Zhong Hong ,  Young-Joon Park ,  Kyle McPherson

IPC: H01L21/768 ,  H01L21/3213

Abstract: A method of fabricating an integrated circuit (IC) includes depositing an aluminum-containing metal interconnect layer at a first temperature over a semiconductor device having a plurality of transistors. The metal interconnect layer is annealed at a maximum annealing temperature that is less than the first temperature. The metal interconnect layer is patterned after the annealing, thereby interconnecting the transistors.

公开(公告)号：US20190221516A1

公开(公告)日：2019-07-18

申请号：US15872429

申请日：2018-01-16

Applicant: Texas Instruments Incorporated

Inventor： Dhishan Kande ,  Qi-Zhong Hong ,  Abbas Ali ,  Gregory B. Shinn

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/768

CPC classification number: H01L23/5228 ,  H01L21/76805 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L28/24

Abstract: A device including a thin film resistor (TFR) structure. The TFR structure is accessible by one or more conductive vias that extend vertically from an upper metal layer to completely penetrate a TFR layer positioned thereunder. The conductive vias are coupled to one or more sidewalls of the TFR layer at or near the sites of penetration. The TFR structure can be manufactured by a method that includes etching a via trench completely through the TFR layer and a dielectric layer above the TFR layer, and filling the via trench with a conductor coupled to a sidewall of the TFR layer.

公开(公告)号：US10211278B2

公开(公告)日：2019-02-19

申请号：US15646917

申请日：2017-07-11

Applicant: Texas Instruments Incorporated

Inventor： Abbas Ali ,  Dhishan Kande ,  Qi-Zhong Hong

IPC: H01L49/02 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/768 ,  H01L21/027 ,  H01L21/02 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532

Abstract: A device and method for fabricating an integrated circuit (IC) chip is disclosed. The method includes depositing a first thin film resistor material on a first inter-level dielectric (ILD) layer; depositing an etch retardant layer overlying the first thin film resistor material; and patterning and etching the etch retardant layer and the first thin film resistor material to form a first resistor. The method continues with depositing a second ILD layer overlying the first resistor; and patterning and etching the second ILD layer using a first etch chemistry to form vias through the second ILD layer and the etch retardant layer to the first resistor. The etch retardant layer is selective to a first etch chemistry and the thickness of the etch retardant layer is such that the via etching process removes substantially all exposed portions of the etch retardant layer and substantially prevents consumption of the underlying first thin film resistor material.

公开(公告)号：US10177214B2

公开(公告)日：2019-01-08

申请号：US15357796

申请日：2016-11-21

Applicant: Texas Instruments Incorporated

Inventor： Abbas Ali ,  Eric Beach

IPC: H01L49/02 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: An integrated circuit with a metal thin film resistor with an overlying etch stop layer. A process for forming a metal thin film resistor in an integrated circuit with the addition of one lithography step.

公开(公告)号：US09793364B2

公开(公告)日：2017-10-17

申请号：US15251443

申请日：2016-08-30

Applicant: Texas Instruments Incorporated

Inventor： David William Hamann ,  Thomas E. Lillibridge ,  Abbas Ali

IPC: H01L29/10 ,  H01L29/40 ,  H01L21/74 ,  H01L29/06

CPC classification number: H01L29/408 ,  H01L21/0212 ,  H01L21/02274 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/743 ,  H01L29/0623 ,  H01L29/401 ,  H01L29/407

Abstract: A semiconductor device with a deep trench has a dielectric liner formed on sidewalls and a bottom of the deep trench. A pre-etch deposition step of a two-step process forms a protective polymer on an existing top surface of the semiconductor device, and on the dielectric liner proximate to a top surface of the substrate. The pre-etch deposition step does not remove a significant amount of the dielectric liner from the bottom of the deep trench. A main etch step of the two-step process removes the dielectric liner at the bottom of the deep trench while maintaining the protective polymer at the top of the deep trench. The protective polymer is subsequently removed.

公开(公告)号：US09337292B1

公开(公告)日：2016-05-10

申请号：US14555359

申请日：2014-11-26

Applicant: Texas Instruments Incorporated

Inventor： Abbas Ali

IPC: H01L23/52 ,  H01L29/45 ,  H01L29/41 ,  H01L29/06 ,  H01L21/02 ,  H01L21/265 ,  H01L21/311

CPC classification number: H01L29/45 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/26513 ,  H01L21/31116 ,  H01L21/743 ,  H01L21/763 ,  H01L29/0684 ,  H01L29/0692 ,  H01L29/41

Abstract: A semiconductor device with a very high aspect ratio contact has a deep trench in the substrate. A dielectric liner is formed on sidewalls and a bottom of the deep trench. A contact opening is formed through the dielectric liner at the bottom of the deep trench to expose the substrate, leaving the dielectric liner on the sidewalls. Electrically conductive material is formed in the deep trench to provide the very high aspect ratio contact to the substrate through the contact opening.

Abstract translation: 具有非常高的纵横比接触的半导体器件在衬底中具有深沟槽。 电介质衬垫形成在深沟槽的侧壁和底部上。 在深沟槽的底部穿过电介质衬垫形成接触开口以露出衬底，将电介质衬垫留在侧壁上。 导电材料形成在深沟槽中，以通过接触开口提供与衬底的非常高的纵横比接触。

公开(公告)号：US09224592B2

公开(公告)日：2015-12-29

申请号：US14473768

申请日：2014-08-29

Applicant: Texas Instruments Incorporated

Inventor： John Christopher Shriner ,  Abbas Ali

IPC: H01L21/20 ,  H01L21/02 ,  H01L21/3213 ,  H01L27/115 ,  H01L49/02 ,  H01L21/311 ,  H01J37/32 ,  H01L21/66

CPC classification number: H01L21/02197 ,  H01J37/32963 ,  H01J2237/334 ,  H01L21/31122 ,  H01L21/32136 ,  H01L21/32139 ,  H01L22/26 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65

Abstract: A method of etching a ferroelectric capacitor stack structure including conductive upper and lower plates with a ferroelectric material, such as lead-zirconium-titanate (PZT), therebetween, with each of these layers defined by the same hard mask element. The stack etch process involves a plasma etch with a fluorine-bearing species as an active species in the etch of the conductive plates, and a non-fluorine-bearing chemistry for etching the PZT ferroelectric material. An example of the fluorine-bearing species is CF4. Endpoint detection can be used to detect the point at which the upper plate etch reaches the PZT, at which point the gases in the chamber are purged to avoid etching the PZT material with fluorine. A steeper sidewall angle for the capacitor structure can be obtained.

Abstract translation: 一种用诸如钛酸锆（PZT）之类的铁电材料的导电上板和下板蚀刻铁电电容器堆叠结构的方法，其中每个层由同一硬掩模元件限定。 堆叠蚀刻工艺包括在导电板的蚀刻中具有含氟物质作为活性物质的等离子体蚀刻和用于蚀刻PZT铁电材料的非含氟化学物质。 含氟物质的实例是CF 4。 可以使用端点检测来检测上板蚀刻到达PZT的点，此时，腔中的气体被清除以避免用氟蚀刻PZT材料。 可以获得电容器结构的更陡的侧壁角。

公开(公告)号：US12170310B2

公开(公告)日：2024-12-17

申请号：US16453796

申请日：2019-06-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Guruvayurappan S. Mathur ,  Abbas Ali ,  Poornika Fernandes ,  Bhaskar Srinivasan ,  Darrell R. Krumme ,  Joao Sergio Afonso ,  Shih-Chang Chang ,  Shariq Arshad

IPC: H01L21/8238 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/06 ,  H01L49/02

Abstract: In some examples, an integrated circuit includes an isolation layer disposed on or over a semiconductor substrate. The integrated circuit also includes a first conductive plate located over the isolation layer and a composite dielectric layer located over the first conductive plate. The composite dielectric layer includes a first sublayer comprising a first chemical composition; a second sublayer comprising a second different chemical composition; and a third sublayer comprising a third chemical composition substantially similar to the first chemical composition. The integrated circuit further includes a second conductive plate located directly on the composite dielectric layer above the first conductive plate.

公开(公告)号：US20240290785A1

公开(公告)日：2024-08-29

申请号：US18176430

申请日：2023-02-28

Applicant: Texas Instruments Incorporated

Inventor： Abbas Ali ,  Bhaskar Srinivasan ,  John Shriner ,  Edmond B. Benton

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823431

Abstract: Forming an integrated circuit by first, forming a first fin and a second fin from a semiconductor layer, with an area between the first fin and the second fin, second, forming a dielectric layer covering at least a portion of the first fin, at least a portion of the second fin, and at least a portion of the area, and third, forming amorphous polysilicon covering a least a portion of the dielectric layer.