公开(公告)号：US20230135889A1

公开(公告)日：2023-05-04

申请号：US17514786

申请日：2021-10-29

Applicant: Texas Instruments Incorporated

Inventor： Abbas Ali ,  Christopher Scott Whitesell ,  John Christopher Shriner ,  Henry Litzmann Edwards

IPC: H01L21/762 ,  H01L27/06 ,  H01L29/78 ,  H01L29/66

Abstract: A method of forming an integrated circuit forms a first oxygen diffusion barrier layer in a fixed position relative to a semiconductor substrate and forms an aperture through the first oxygen diffusion barrier layer to expose a portion of the semiconductor substrate. The method also forms a first LOCOS region in an area of the aperture and a second oxygen diffusion barrier layer along the first LOCOS region and along at least a sidewall portion of the first oxygen diffusion barrier layer in the area of the aperture. The method also deposits a polysilicon layer, at a temperature of 570° C. or less, over the second oxygen diffusion barrier layer, etches the polysilicon layer and the second oxygen diffusion barrier layer to form a spacer in the area of the aperture, and forms a second LOCOS region in the area of the aperture and aligned to the spacer.

公开(公告)号：US11984362B1

公开(公告)日：2024-05-14

申请号：US17411761

申请日：2021-08-25

Applicant: Texas Instruments Incorporated

Inventor： Abbas Ali ,  Christopher Scott Whitesell ,  John Christopher Shriner ,  Henry Litzmann Edwards

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823462 ,  H01L27/088

Abstract: A method of fabricating an integrated circuit includes forming a first opening having a first width and a second opening having a second width in a first dielectric layer over a silicon substrate. The openings expose the silicon substrate and the exposed silicon substrate is oxidized to form first and second LOCOS structures having a first thickness. A polysilicon layer is formed over the silicon substrate, so that the polysilicon layer fills the first and second openings. A blanket etch of the polysilicon layer is performed to remove at least a portion of the polysilicon layer over the second LOCOS structure while leaving the first LOCOS structure protected by the polysilicon layer. The silicon substrate under the second LOCOS structure is further oxidized such that the second LOCOS structure has a second thickness greater than the first thickness.

公开(公告)号：US20150072443A1

公开(公告)日：2015-03-12

申请号：US14473768

申请日：2014-08-29

Applicant: Texas Instruments Incorporated

Inventor： John Christopher Shriner ,  Abbas Ali

IPC: H01L49/02 ,  H01L21/3213 ,  H01L21/02 ,  H01L21/033

CPC classification number: H01L21/02197 ,  H01J37/32963 ,  H01J2237/334 ,  H01L21/31122 ,  H01L21/32136 ,  H01L21/32139 ,  H01L22/26 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65

Abstract: A method of etching a ferroelectric capacitor stack structure including conductive upper and lower plates with a ferroelectric material, such as lead-zirconium-titanate (PZT), therebetween, with each of these layers defined by the same hard mask element. The stack etch process involves a plasma etch with a fluorine-bearing species as an active species in the etch of the conductive plates, and a non-fluorine-bearing chemistry for etching the PZT ferroelectric material. An example of the fluorine-bearing species is CF4. Endpoint detection can be used to detect the point at which the upper plate etch reaches the PZT, at which point the gases in the chamber are purged to avoid etching the PZT material with fluorine. A steeper sidewall angle for the capacitor structure can be obtained.

Abstract translation: 一种用诸如钛酸锆（PZT）之类的铁电材料的导电上板和下板蚀刻铁电电容器堆叠结构的方法，其中每个层由同一硬掩模元件限定。 堆叠蚀刻工艺包括在导电板的蚀刻中具有含氟物质作为活性物质的等离子体蚀刻和用于蚀刻PZT铁电材料的非含氟化学物质。 含氟物质的实例是CF 4。 可以使用端点检测来检测上板蚀刻到达PZT的点，此时，腔中的气体被清除以避免用氟蚀刻PZT材料。 可以获得电容器结构的更陡的侧壁角。

公开(公告)号：US20170133284A1

公开(公告)日：2017-05-11

申请号：US14934113

申请日：2015-11-05

Applicant: Texas Instruments Incorporated

Inventor： John Christopher Shriner

IPC: H01L21/66

CPC classification number: H01J37/32862 ,  H01J37/32935 ,  H01J37/32963 ,  H01J37/32972 ,  H01J37/32981

Abstract: A microelectronic device is formed using a fabrication tool such as a plasma thin film deposition tool or a plasma etch tool. A smart in-situ chamber clean begins with an initial plasma. A first physical signal is measured while the initial plasma is in progress, and the measured value is stored in a memory unit. A process controller retrieves the measured value, uses it to compute a deposition estimate parameter, and determines when the deposition estimate parameter meets a minimum deposition criterion. When the result of the determination is TRUE, the smart in-situ chamber clean terminates without an in-situ cleaning of the process chamber. When the result of the determination is FALSE, the smart in-situ chamber clean proceeds with an in-situ cleaning. The in-situ cleaning may be a continuation of the initial plasma. Subsequently, the microelectronic device is processed in the fabrication tool.

公开(公告)号：US20240258175A1

公开(公告)日：2024-08-01

申请号：US18632439

申请日：2024-04-11

Applicant: Texas Instruments Incorporated

Inventor： Abbas Ali ,  Christopher Scott Whitesell ,  John Christopher Shriner ,  Henry Litzmann Edwards

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/823462 ,  H01L27/088

Abstract: A method of fabricating an integrated circuit includes forming a first opening having a first width and a second opening having a second width in a first dielectric layer over a silicon substrate. The openings expose the silicon substrate and the exposed silicon substrate is oxidized to form first and second LOCOS structures having a first thickness. A polysilicon layer is formed over the silicon substrate, so that the polysilicon layer fills the first and second openings. A blanket etch of the polysilicon layer is performed to remove at least a portion of the polysilicon layer over the second LOCOS structure while leaving the first LOCOS structure protected by the polysilicon layer. The silicon substrate under the second LOCOS structure is further oxidized such that the second LOCOS structure has a second thickness greater than the first thickness.

公开(公告)号：US10923406B2

公开(公告)日：2021-02-16

申请号：US16712234

申请日：2019-12-12

Applicant: Texas Instruments Incorporated

Inventor： John Christopher Shriner ,  Maja Imamovic ,  Kevin Paul Wiederhold

IPC: H01L21/00 ,  H01L21/66 ,  H01L21/67 ,  H01J37/32

Abstract: A plasma processing tool for fabricating a semiconductor device on a semiconductor wafer includes an optical window disposed on a plasma chamber, remotely from a plasma region. The window is thermally connected to an electrical heater element capable of maintaining the window at a temperature of at least 30° C. A heater controller provides electrical power to the heater element. During operation of the plasma processing tool, the heater controller provides power to the heater element so as to maintain the window at a temperature of at least 30° C. during at least a portion of a plasma process step in which by-products are produced in the plasma chamber.

公开(公告)号：US20180068908A1

公开(公告)日：2018-03-08

申请号：US15796114

申请日：2017-10-27

Applicant: Texas Instruments Incorporated

Inventor： John Christopher Shriner

IPC: H01L21/66 ,  H01J37/32

CPC classification number: H01J37/32862 ,  H01J37/32935 ,  H01J37/32963 ,  H01J37/32972 ,  H01J37/32981

Abstract: A microelectronic device is formed using a fabrication tool such as a plasma thin film deposition tool or a plasma etch tool. A smart in-situ chamber clean begins with an initial plasma. A first physical signal is measured while the initial plasma is in progress, and the measured value is stored in a memory unit. A process controller retrieves the measured value, uses it to compute a deposition estimate parameter, and determines when the deposition estimate parameter meets a minimum deposition criterion. When the result of the determination is TRUE, the smart in-situ chamber clean terminates without an in-situ cleaning of the process chamber. When the result of the determination is FALSE, the smart in-situ chamber clean proceeds with an in-situ cleaning. The in-situ cleaning may be a continuation of the initial plasma. Subsequently, the microelectronic device is processed in the fabrication tool.

公开(公告)号：US09224592B2

公开(公告)日：2015-12-29

申请号：US14473768

申请日：2014-08-29

Applicant: Texas Instruments Incorporated

Inventor： John Christopher Shriner ,  Abbas Ali

IPC: H01L21/20 ,  H01L21/02 ,  H01L21/3213 ,  H01L27/115 ,  H01L49/02 ,  H01L21/311 ,  H01J37/32 ,  H01L21/66

CPC classification number: H01L21/02197 ,  H01J37/32963 ,  H01J2237/334 ,  H01L21/31122 ,  H01L21/32136 ,  H01L21/32139 ,  H01L22/26 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65

Abstract: A method of etching a ferroelectric capacitor stack structure including conductive upper and lower plates with a ferroelectric material, such as lead-zirconium-titanate (PZT), therebetween, with each of these layers defined by the same hard mask element. The stack etch process involves a plasma etch with a fluorine-bearing species as an active species in the etch of the conductive plates, and a non-fluorine-bearing chemistry for etching the PZT ferroelectric material. An example of the fluorine-bearing species is CF4. Endpoint detection can be used to detect the point at which the upper plate etch reaches the PZT, at which point the gases in the chamber are purged to avoid etching the PZT material with fluorine. A steeper sidewall angle for the capacitor structure can be obtained.

Abstract translation: 一种用诸如钛酸锆（PZT）之类的铁电材料的导电上板和下板蚀刻铁电电容器堆叠结构的方法，其中每个层由同一硬掩模元件限定。 堆叠蚀刻工艺包括在导电板的蚀刻中具有含氟物质作为活性物质的等离子体蚀刻和用于蚀刻PZT铁电材料的非含氟化学物质。 含氟物质的实例是CF 4。 可以使用端点检测来检测上板蚀刻到达PZT的点，此时，腔中的气体被清除以避免用氟蚀刻PZT材料。 可以获得电容器结构的更陡的侧壁角。