公开(公告)号：US10002774B1

公开(公告)日：2018-06-19

申请号：US15697098

申请日：2017-09-06

Applicant: Texas Instruments Incorporated

Inventor： Abbas Ali ,  Dhishan Kande ,  Qi-Zhong Hong ,  Young-Joon Park ,  Kyle McPherson

IPC: H01L21/44 ,  H01L21/3213 ,  H01L21/768

CPC classification number: H01L21/32136 ,  H01L21/76819 ,  H01L21/76837 ,  H01L21/76841 ,  H01L21/76885 ,  H01L23/53223

Abstract: A method of fabricating an integrated circuit (IC) includes forming a metal interconnect stack on substrate that includes a plurality of product die each having a plurality of transistors connected together to implement a circuit function. The forming the metal interconnect stack includes depositing a metal interconnect layer comprising aluminum on a barrier layer at a first temperature. After depositing the metal interconnect layer, the metal interconnect stack is annealed in a non-oxidizing ambient at a maximum annealing temperature that is

公开(公告)号：US09157938B2

公开(公告)日：2015-10-13

申请号：US13668586

申请日：2012-11-05

Applicant: Texas Instruments Incorporated

Inventor： Young-Joon Park ,  Siva Prakash Gurrum

IPC: G06F19/00 ,  G01R19/04

CPC classification number: G01R19/04

Abstract: A method of computing a peak current density specification (jpeakspec) for an electrical conductor line of an integrated circuit (IC) resulting from conducting pulsed electrical current represented as a current waveform. An on-time (ton) is identified for the current waveform based on a current density being greater than or equal to (≧) a predetermined current density level. The jpeakspec is computed for the electrical conductor line using a jpeakspec modeling equation which includes the ton for the current waveform and a thermal time constant (τ) for the electrical conductor line.

Abstract translation: 计算通过表示为电流波形的脉冲电流导致的集成电路（IC）的导电线的峰值电流密度规格（jpeakspec）的方法。 基于大于或等于（≥）预定电流密度级的电流密度，为当前波形识别导通时间（ton）。 使用jpeakspec建模方程计算电导体线的jpeakspec，该方程包括电流波形的ton和电导体线的热时间常数（τ）。

公开(公告)号：US12027468B2

公开(公告)日：2024-07-02

申请号：US17176995

申请日：2021-02-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jungwoo Joh ,  Young-Joon Park

IPC: H01L23/552 ,  H01L21/48 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/78 ,  H05K1/02

CPC classification number: H01L23/552 ,  H01L21/486 ,  H01L21/76802 ,  H01L23/5226 ,  H01L23/53228 ,  H01L29/7816 ,  H05K1/0216

Abstract: A semiconductor device a strapped interconnect line, which in turn includes a first interconnect line at a first level above a semiconductor substrate, and a second interconnect line at a second level above the interconnect substrate. A dielectric capping layer is located directly on the first interconnect line. A plurality of strapping vias are connected between the first interconnect line and the second interconnect line. Each of the strapping vias extends from a first side of the first interconnect line to a second side of the second interconnect line.

公开(公告)号：US10361095B2

公开(公告)日：2019-07-23

申请号：US15981725

申请日：2018-05-16

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abbas Ali ,  Dhishan Kande ,  Qi-Zhong Hong ,  Young-Joon Park ,  Kyle McPherson

IPC: H01L21/768 ,  H01L21/3213

Abstract: A method of fabricating an integrated circuit (IC) includes depositing an aluminum-containing metal interconnect layer at a first temperature over a semiconductor device having a plurality of transistors. The metal interconnect layer is annealed at a maximum annealing temperature that is less than the first temperature. The metal interconnect layer is patterned after the annealing, thereby interconnecting the transistors.