PEAK DETECTOR CIRCUIT
    1.
    发明申请

    公开(公告)号:US20190138758A1

    公开(公告)日:2019-05-09

    申请号:US15808607

    申请日:2017-11-09

    摘要: A peak detector circuit includes a first capacitor coupled to an inverter and a first switch in parallel with the inverter. An input of the inverter couples to second and third switches. The second switch couples to an input voltage node. The third switch couples to an output voltage node of the peak detector circuit. The peak detector circuit includes a second capacitor coupled to the third switch and a third capacitor coupled to the second capacitor by way of a fourth switch. The third capacitor couples via a fifth switch to a power supply voltage node or a ground. A periodic control signal causes the first, second, and third switches to repeatedly open and close and a second control signal causes the fourth and fifth switches to open and close to adjust an output voltage on the output voltage node towards an input voltage on the input voltage node.

    VOLTAGE DETECTION CIRCUIT
    4.
    发明申请

    公开(公告)号:US20180131337A1

    公开(公告)日:2018-05-10

    申请号:US15730918

    申请日:2017-10-12

    申请人: DENSO CORPORATION

    发明人: Kazutaka HONDA

    摘要: A voltage detection circuit includes two detection capacitors, which are paired and configured differentially, first to third detection switches, a drive part, a minimum selector and a maximum selector. The first detection switch is formed of a pMOS transistor, which opens and closes a path between one of the detection capacitors and an input node. The second detection switch is formed of an nMOS transistor, which opens and closes a path between the other of the detection capacitors and an input node. The third detection switch is formed of a series circuit of a pMOS transistor and an nMOS transistor, which open and close a path between two detection capacitors. The driving part turns on and off complementarily between the first and second switches and the third detection switch. The minimum selector applies a lower one of voltages of the input nodes as a substrate potential of the nMOS transistor. The maximum selector applies a higher one of the voltages of the input nodes as a substrate potential of the pMOS transistor.

    Hand-held Voltmeter for Electric Fence
    7.
    发明申请

    公开(公告)号:US20170343590A1

    公开(公告)日:2017-11-30

    申请号:US15247971

    申请日:2016-08-26

    申请人: Byung-Hak Cho

    发明人: Byung-Hak Cho

    IPC分类号: G01R19/04 G01R13/00

    CPC分类号: G01R19/04 G01R19/0084

    摘要: The present disclosure relates to a hand-held voltmeter measuring a peak voltage of a high voltage pulse applied to an electric fence. The voltmeter includes a body case of which one side has an opening, a sensor case protruded from the opening of the body case, a voltage divider disposed over the inside and the outside of the sensor case for dividing the high voltage pulse into a low divided voltage, a peak detector for detecting the peak voltage of the divided voltage, a display unit for displaying the peak voltage, and an MCU for controlling the input and the output of the elements constituting the voltmeter. According to the present disclosure, an electric fence voltmeter that measures the peak voltage accurately without need to make a ground connection to the earth, and has a low risk of an electric shock during a measurement is provided.

    FAST CURRENT-BASED ENVELOPE DETECTOR
    8.
    发明申请

    公开(公告)号:US20170343589A1

    公开(公告)日:2017-11-30

    申请号:US15163380

    申请日:2016-05-24

    IPC分类号: G01R19/04

    摘要: A reduced-stage feedback-based envelope detector includes, for example, an input rectifier for rectifying a received modulated input signal and an amplifier for receiving the rectified modulated input signal at an input node. The amplifier compares the rectified modulated input signal with a reference signal, filters the rectified modulated input signal at the input node, and generates an envelope detection signal in response to the comparison and the filtering of the rectified modulated input signal. In an embodiment, the gain of the amplifier is independently determined from the bandwidth of the amplifier.

    mm-Wave frequency peak detector
    9.
    发明授权

    公开(公告)号:US09817041B2

    公开(公告)日:2017-11-14

    申请号:US15027272

    申请日:2013-10-18

    申请人: Yi Yin

    发明人: Yi Yin

    IPC分类号: G01R19/04 G01R21/01

    摘要: A peak detector circuit comprises a first output coupled to ground by a first load and to emitter terminals of first and second switching devices. A second output is coupled to ground by a second load and to emitter terminals of third and fourth switching devices. A third output is coupled to a supply voltage node by a third load and to collector terminals of the first and second switching devices. A fourth output is coupled to the supply voltage node by a fourth load and to collector terminals of the third and fourth switching devices. The first, second, third, and fourth switching devices have control terminals which are biased with a common bias voltage. The first, second, third and fourth load are selected so that R1=R2=αf*R3=αf*R4, with R1, R2, R3, R4 being a resistance of the first, second, third and fourth loads, respectively, and αf a common-base current gain of the switching devices.

    Method of implementation of peak hold in a phasing voltmeter

    公开(公告)号:US09804204B2

    公开(公告)日:2017-10-31

    申请号:US13238418

    申请日:2011-09-21

    摘要: A high voltage phasing voltmeter comprises first and second probes. Each probe comprises an electrode for contacting a high voltage electrical conductor. The electrodes are connected in series with a resistor. A meter comprises a housing enclosing an electrical circuit for measuring true rms voltage. The electrical circuit comprises an input circuit for connection to the first and second probes and developing a scaled voltage representing measured voltage across the electrodes. A converter circuit converts the scaled voltage to a DC signal representing true rms value of the measured voltage. A peak hold circuit is connected to the converter circuit to hold a peak value of the true rms value. A display is connected to the peak hold circuit for displaying the peak value of the true rms value.