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公开(公告)号：US11990831B2
公开(公告)日：2024-05-21
申请号：US17875797
申请日：2022-07-28
发明人： Holger Petersen
CPC分类号： H02M1/0095 , H02M3/07
摘要： A buck-boost power converter is operable in a first mode (step-down) or in a second mode (step-up). The power converter has an inductor, a flying capacitor, a network of six switches and a driver adapted to drive the network of switches with a sequence of states. Depending on the mode of operation the sequence of states comprises at least one of a first state and a second state. In the first state the ground port is coupled to the second port via two paths, a first path comprising the flying capacitor and the inductor, and a second path comprising the flying capacitor while bypassing the inductor. In the second state the first port is coupled to the second port via a path that includes the inductor and the ground port is coupled to the first port via a path that includes the flying capacitor while bypassing the inductor.
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公开(公告)号：US11863081B2
公开(公告)日：2024-01-02
申请号：US16669909
申请日：2019-10-31
发明人： Santosh Kulkarni , Jens Masuch
CPC分类号： H02M5/293 , H01F3/14 , H01F27/2804
摘要： A single/Multi-phase PMIC built on silicon substrate with coil layers processed on top of the PMIC layers' is provided. The integrated coil is in a spiral form, with a gap at the center of the coil, making additional metal routing not required. The integrated coil has connection pads located in the center gap of the spiral form, limiting the overall inductor resistance to the device only. The on-die inductor may have a magnetic core wrapping the windings. The spiral form may be implemented in a circular design, or a racetrack (elongated spiral) design. The coil layers may be implemented as multiple coil layers or as a single coil layer, connected in parallel (with the same I/O pads), reducing the resistance and maintaining the inductance.
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公开(公告)号：US11860199B2
公开(公告)日：2024-01-02
申请号：US17226526
申请日：2021-04-09
发明人： Francesco Paolo , Ambreesh Bhattad
IPC分类号： G01R19/15 , G01R19/165
CPC分类号： G01R19/15 , G01R19/16547
摘要： An apparatus for a first current sensor for a switching converter has an inductor and a first switch. The first switch is arranged to selectively couple the inductor to a first voltage. The first current sensor generates a first output current that is dependent on an inductor current flowing through the inductor The first current sensor compensates for an error arising due to the first switch in the generation of the first output current. The apparatus provides an improved current sensor for a switching converter that overcomes or mitigates the problem of errors in the measurement of a current.
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公开(公告)号：US20230387788A1
公开(公告)日：2023-11-30
申请号：US17828159
申请日：2022-05-31
发明人： Yu-Chin LIN
IPC分类号： H02M1/14 , H02M1/42 , H05B45/3725 , H05B45/355 , H05B45/36
CPC分类号： H02M1/143 , H02M1/4258 , H05B45/3725 , H05B45/355 , H05B45/36
摘要： A ripple reduction circuit for use with an AC/DC power supply providing an output voltage to a load is presented. The ripple reduction circuit includes an input terminal for receiving the output voltage and a low pass filter. The low pass filter is used to filter an AC component of the output voltage to obtain a filtered DC voltage. The ripple reduction circuit generates a reference current based on the filtered DC voltage and a control voltage having an AC component in phase with the AC component of the output voltage.
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公开(公告)号：US11817952B2
公开(公告)日：2023-11-14
申请号：US17588832
申请日：2022-01-31
IPC分类号： H04L1/00 , H04L61/2503
CPC分类号： H04L1/0063 , H04L1/0043 , H04L1/0052 , H04L61/2503
摘要： A system for providing end-to-end data protection between a transmitting end device and a receiving end device is presented. The system has a transmitting end device to calculate a first check value for a first message, which has first and second data blocks; the receiving end device; and a remapping device. The remapping device is configured to remap a data block among the first and second data blocks for generating a second message for the receiving end device. The remapping device also determines a remapping value based on the data block and the remapped data block, such that a second check value that would be calculated for the second message would be equal to the first check value, and wherein the second message comprises the other one of the first and second data blocks, the remapped data block, and the remapping value.
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公开(公告)号：US11669666B1
公开(公告)日：2023-06-06
申请号：US17106965
申请日：2020-11-30
发明人： Dantes John , Stefano Rachiele
IPC分类号： G06F30/30 , G06F30/35 , G06F30/3308 , G06F30/33 , G06F30/323
CPC分类号： G06F30/35 , G06F30/33 , G06F30/3308 , G06F30/323
摘要： A method for determining one or more tests suitable for verifying that a circuit conforms to a specification is presented. The specification has at least one state machine. Example circuits are asynchronous circuits. The method includes analysing the specification to automatically determine the one or more tests for circuit verification.
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公开(公告)号：US20230122225A1
公开(公告)日：2023-04-20
申请号：US17501151
申请日：2021-10-14
发明人： Mark Mercer
IPC分类号： H02M3/07
摘要： The present document describes a power converter configured to convert electrical power at an input voltage at an input of the power converter to electrical power at an output voltage at an output of the power converter. The power converter comprises a first flying capacitor, a second flying capacitor and a third flying capacitor, as well as an inductor and a set of power switches. Furthermore, the power converter comprises a control unit configured to control the set of power switches such that during an operation cycle the power converter is operated in a first state and in a second state in a mutually exclusive manner.
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公开(公告)号：US11626800B2
公开(公告)日：2023-04-11
申请号：US17308271
申请日：2021-05-05
发明人： Francesco Cannillo , Nicola Macri
摘要： A power converter and method to provide a small conversion ratio between an input and an output voltage. The power converter has an inductor coupled to the input port of the power converter. The power converter has a first stage with an input node; a first switch; a second switch; a third switch coupled to the second switch of the first stage and to a reference potential; and a flying capacitor coupled to the input node. The power converter also has a second stage with an input node; a first switch coupled to the input node of the second stage and to the output port of the power converter; a second switch coupled to the input node of the first stage; a third switch coupled to the second switch of the second stage and to the reference potential; and a flying capacitor coupled to the inductor.
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公开(公告)号：US11611284B2
公开(公告)日：2023-03-21
申请号：US17344281
申请日：2021-06-10
发明人： Yu-Chin Lin
IPC分类号： H02M3/335
摘要： An isolated switching power converter is presented. The isolated switching converter includes a transformer, a secondary-side switch and a secondary-side controller. The transformer has a primary winding coupled to an input, a first secondary winding coupled to a first output for providing a first output voltage, and a second secondary winding coupled to a second output for providing a second output voltage. The secondary-side switch is coupled to the second secondary winding. The secondary-side controller compares the second output voltage with a first reference voltage and generates a control signal based on the comparison to operate the secondary-side switch.
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10.发明申请公开(公告)号：US20230077469A1
公开(公告)日：2023-03-16
申请号：US17967472
申请日：2022-10-17
摘要： A multi-pin wafer level chip scale package is achieved. One or more solder pillars and one or more solder blocks are formed on a silicon wafer wherein the one or more solder pillars and the one or more solder blocks all have a top surface in a same horizontal plane. A pillar metal layer underlies the one or more solder pillars and electrically contacts the one or more solder pillars with the silicon wafer through an opening in a polymer layer over a passivation layer. A block metal layer underlies the one or more solder blocks and electrically contacts the one or more solder pillars with the silicon wafer through a plurality of via openings through the polymer layer over the passivation layer wherein the block metal layer is thicker than the pillar metal layer.
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