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    Reduction of cross talk in WLCSP's through laser drilled technique
    2.
    发明授权
    Reduction of cross talk in WLCSP's through laser drilled technique 有权

    公开(公告)号：US10396004B2

    公开(公告)日：2019-08-27

    申请号：US15879904

    申请日：2018-01-25

    Applicant: Dialog Semiconductor (UK) Limited

    Inventor： Habeeb Mohiuddin Mohammed ,  Rajesh Subraya Aiyandra

    IPC: H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L29/06 ,  B81C1/00 ,  H01L21/56

    Abstract: A wafer level chip scale package is described. The wafer level chip scale package comprises a plurality of redistribution layer (RDL) traces connected to a silicon wafer through openings through a first polymer layer to metal pads on a top surface of the silicon wafer. A plurality of underbump metal (UBM) layers each contact one of the plurality of RDL traces through openings in a second polymer layer over the first polymer layer. A plurality of solder bumps lie on each UBM layer. A metal plating layer lies under the first polymer layer and does not contact any of the plurality of RDL traces. At least one separator lies between at least two of the plurality of RDL traces. The separator is a metal fencing between the two neighboring RDL traces or an air gap between the two neighboring RDL traces.

    Re-Routable Clip for Leadframe Based Product
    3.
    发明申请
    Re-Routable Clip for Leadframe Based Product 审中-公开

    公开(公告)号：US20190259689A1

    公开(公告)日：2019-08-22

    申请号：US15899049

    申请日：2018-02-19

    Applicant: Dialog Semiconductor (UK) Limited

    Inventor： Tung Ching Lui ,  Baltazar Canete ,  Melvin Martin ,  Rajesh Subraya Aiyandra

    IPC: H01L23/495 ,  H01L23/498 ,  H05K1/02

    Abstract: A method of fabricating an integrated circuit package having improved heat dissipation is described. A re-routable clip is provided having a central portion and a plurality of leads surrounding the central portion. A die is attached to an underside of the central portion of the re-routable clip. The die and the leads of the re-routable clip are attached to a substrate. The die and the leads are encapsulated with a mold compound wherein a top surface of the central portion of the re-routable clip is exposed by the mold compound. The substrate is connected to a printed circuit board wherein thermal pathways are formed 1) from the die downward to the substrate to the printed circuit board and 2) from the die upward to the re-routable clip and then downward through the leads to the substrate and to the printed circuit board.

    Multi-pin-wafer-level-chip-scale-packaging solution for high power semiconductor devices
    4.
    发明授权
    Multi-pin-wafer-level-chip-scale-packaging solution for high power semiconductor devices 有权

    公开(公告)号：US10797012B2

    公开(公告)日：2020-10-06

    申请号：US15686484

    申请日：2017-08-25

    Applicant: Dialog Semiconductor (UK) Limited

    Inventor： Habeeb Mohiuddin Mohammed ,  Rajesh Subraya Aiyandra

    IPC: H01L23/00 ,  H01L23/31

    Abstract: A multi-pin wafer level chip scale package is achieved. One or more solder pillars and one or more solder blocks are formed on a silicon wafer wherein the one or more solder pillars and the one or more solder blocks all have a top surface in a same horizontal plane. A pillar metal layer underlies the one or more solder pillars and electrically contacts the one or more solder pillars with the silicon wafer through an opening in a polymer layer over a passivation layer. A block metal layer underlies the one or more solder blocks and electrically contacts the one or more solder pillars with the silicon wafer through a plurality of via openings through the polymer layer over the passivation layer wherein the block metal layer is thicker than the pillar metal layer.

    Multi-Pin-Wafer-Level-Chip-Scale-Packaging Solution for High Power Semiconductor Devices
    6.
    发明申请
    Multi-Pin-Wafer-Level-Chip-Scale-Packaging Solution for High Power Semiconductor Devices 审中-公开

    公开(公告)号：US20190067229A1

    公开(公告)日：2019-02-28

    申请号：US15686484

    申请日：2017-08-25

    Applicant: Dialog Semiconductor (UK) Limited

    Inventor： Habeeb Mohiuddin Mohammed ,  Rajesh Subraya Aiyandra

    IPC: H01L23/00 ,  H01L23/31

    Abstract: A multi-pin wafer level chip scale package is achieved. One or more solder pillars and one or more solder blocks are formed on a silicon wafer wherein the one or more solder pillars and the one or more solder blocks all have a top surface in a same horizontal plane. A pillar metal layer underlies the one or more solder pillars and electrically contacts the one or more solder pillars with the silicon wafer through an opening in a polymer layer over a passivation layer. A block metal layer underlies the one or more solder blocks and electrically contacts the one or more solder pillars with the silicon wafer through a plurality of via openings through the polymer layer over the passivation layer wherein the block metal layer is thicker than the pillar metal layer.

    Multi-Pin-Wafer-Level-Chip-Scale-Packaging Solution for High Power Semiconductor Devices
    7.
    发明申请
    Multi-Pin-Wafer-Level-Chip-Scale-Packaging Solution for High Power Semiconductor Devices 有权

    公开(公告)号：US20230077469A1

    公开(公告)日：2023-03-16

    申请号：US17967472

    申请日：2022-10-17

    Applicant: Dialog Semiconductor (UK) Limited

    Inventor： Habeeb Mohiuddin Mohammed ,  Rajesh Subraya Aiyandra

    IPC: H01L23/00 ,  H01L23/31

    Abstract: A multi-pin wafer level chip scale package is achieved. One or more solder pillars and one or more solder blocks are formed on a silicon wafer wherein the one or more solder pillars and the one or more solder blocks all have a top surface in a same horizontal plane. A pillar metal layer underlies the one or more solder pillars and electrically contacts the one or more solder pillars with the silicon wafer through an opening in a polymer layer over a passivation layer. A block metal layer underlies the one or more solder blocks and electrically contacts the one or more solder pillars with the silicon wafer through a plurality of via openings through the polymer layer over the passivation layer wherein the block metal layer is thicker than the pillar metal layer.

    Multi-pin-wafer-level-chip-scale-packaging solution for high power semiconductor devices
    8.
    发明授权
    Multi-pin-wafer-level-chip-scale-packaging solution for high power semiconductor devices 有权

    公开(公告)号：US11495567B2

    公开(公告)日：2022-11-08

    申请号：US16995697

    申请日：2020-08-17

    Applicant: Dialog Semiconductor (UK) Limited

    Inventor： Habeeb Mohiuddin Mohammed ,  Rajesh Subraya Aiyandra

    IPC: H01L23/31 ,  H01L23/00

    Abstract: A multi-pin wafer level chip scale package is achieved. One or more solder pillars and one or more solder blocks are formed on a silicon wafer wherein the one or more solder pillars and the one or more solder blocks all have a top surface in a same horizontal plane. A pillar metal layer underlies the one or more solder pillars and electrically contacts the one or more solder pillars with the silicon wafer through an opening in a polymer layer over a passivation layer. A block metal layer underlies the one or more solder blocks and electrically contacts the one or more solder pillars with the silicon wafer through a plurality of via openings through the polymer layer over the passivation layer wherein the block metal layer is thicker than the pillar metal layer.

    Reduction of cross talk in WLCSP's through laser drilled technique
    10.
    发明授权
    Reduction of cross talk in WLCSP's through laser drilled technique 有权

    公开(公告)号：US10607912B2

    公开(公告)日：2020-03-31

    申请号：US16525702

    申请日：2019-07-30

    Applicant: Dialog Semiconductor (UK) Limited

    Inventor： Habeeb Mohiuddin Mohammed ,  Rajesh Subraya Aiyandra

    IPC: H01L23/31 ,  H01L21/56 ,  H01L23/498 ,  H01L23/00 ,  H01L29/06 ,  B81C1/00

    Abstract: A wafer level chip scale package is described. The wafer level chip scale package comprises a plurality of redistribution layer (RDL) traces connected to a silicon wafer through openings through a first polymer layer to metal pads on a top surface of the silicon wafer. A plurality of underbump metal (UBM) layers each contact one of the plurality of RDL traces through openings in a second polymer layer over the first polymer layer. A plurality of solder bumps lie on each UBM layer. A metal plating layer lies under the first polymer layer and does not contact any of the plurality of RDL traces. At least one separator lies between at least two of the plurality of RDL traces. The separator is a metal fencing between the two neighboring RDL traces or an air gap between the two neighboring RDL traces.

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