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公开(公告)号：US11482928B2
公开(公告)日：2022-10-25
申请号：US16731593
申请日：2019-12-31
发明人： Rebecca Tristram , Mark Childs , Jens Masuch
摘要： A solution is provided for adaptive slope compensation in a DC-DC switching converter. Jitter is reduced for on times less than 50% Tpd by using two or more different slopes for the compensation ramp. Additionally, any discontinuities at the 50% duty cycle point are reduced. Details of the compensation ramp are described, where the ramp rate for the first half of the switching period, for on times greater than 50% Tpd, decreases with increasing on time until, at an on time of 100% Tpd, it is approximately zero. In addition, the ramp rate for the second half of the switching period, for on times greater than 50% Tpd, decreases with decreasing on time until, at a duty of 50%, it is equal to the ramp rate used for the first half of the switching period.
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公开(公告)号：US10963032B2
公开(公告)日：2021-03-30
申请号：US16371561
申请日：2019-04-01
发明人： Frank Kronmueller , Mark Childs , Ahmed Shaban
摘要： A power supply and a method to provide power to a load via a power delivery network are presented. The power delivery network adds a pole and/or zero to a transfer function of the power supply. The power supply has a feedback unit to sense a load voltage at the load and to provide a feedback voltage which is indicative of the load voltage. The power supply has an input amplifier provides an error voltage based on the feedback voltage. The power supply has a power converter to provide power to the power delivery network depending on the error voltage. The power supply has an equalization unit to add a zero and/or a pole to the transfer function of the power supply, such that the pole and/or zero of the power delivery network is partially compensated. The equalization unit is located between an input amplifier and a power converter.
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3.发明申请公开(公告)号：US20210044205A1
公开(公告)日：2021-02-11
申请号：US17076973
申请日：2020-10-22
发明人： Mark Childs , Jens Masuch
摘要： The clock input of a buck converter is delayed, preventing sub-harmonic oscillation. The function may be achieved by implementing a clock delay generation circuit, configured to delay a next clock pulse by an amount of time directly proportional to the most recent on time of the high-side switch for peak-mode current control, inversely proportional to the most recent on time of the low-side switch for peak-mode current control, inversely proportional to the most recent on time of the high-side switch for valley-mode current control, or inversely proportional to the clock minus the most recent on time of the high-side switch for valley-mode current control.
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公开(公告)号：US20200052591A1
公开(公告)日：2020-02-13
申请号：US16658743
申请日：2019-10-21
发明人： Pietro Gallina , Vincenzo Bisogno , Mark Childs
摘要： An object of this disclosure is to implement a Buck, Boost, or other switching converter, with a circuit to supply a reference voltage and Adaptive Voltage Positioning (AVP), by means of a servo and programmable load regulation. The reference voltage is modified, achieving a high DC gain, using a servo to remove any DC offset at the output of the switching converter. The correction implemented by the servo is measured, and a programmable fraction of the correction is injected back on either the reference voltage or the output feedback voltage. To accomplish at least one of these objects, a Buck, Boost, or other switching converter is implemented, consisting of an output stage driven by switching logic, with a servo configured between the reference voltage and the control loops of the Buck converter. The AVP function is implemented on either the reference voltage or output feedback voltage.
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公开(公告)号：US20190384372A1
公开(公告)日：2019-12-19
申请号：US16371561
申请日：2019-04-01
发明人： Frank Kronmueller , Mark Childs , Ahmed Shaban
IPC分类号： G06F1/3209 , H02J3/14
摘要： A power supply and a method to provide power to a load via a power delivery network are presented. The power delivery network adds a pole and/or zero to a transfer function of the power supply. The power supply has a feedback unit to sense a load voltage at the load and to provide a feedback voltage which is indicative of the load voltage. The power supply has an input amplifier provides an error voltage based on the feedback voltage. The power supply has a power converter to provide power to the power delivery network depending on the error voltage. The power supply has an equalization unit to add a zero and/or a pole to the transfer function of the power supply, such that the pole and/or zero of the power delivery network is partially compensated. The equalization unit is located between an input amplifier and a power converter.
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公开(公告)号：US10205389B2
公开(公告)日：2019-02-12
申请号：US15596399
申请日：2017-05-16
发明人： Mark Childs , Paul Collins
摘要： A switching mode power supply (SMPS) configured for clearing an overvoltage condition. The overvoltage is determined by detecting that the output voltage has exceeded the input voltage by a limited amount. The overvoltage is cleared by repetitively turning on and then off the switches controlling the flow of energy to the SMPS in sequence until the excess charge resulting from the overvoltage is couple to circuit ground, and the output is reduced to within acceptable limits.
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公开(公告)号：US20180342952A1
公开(公告)日：2018-11-29
申请号：US15604718
申请日：2017-05-25
发明人： Mark Childs , Jens Masuch
摘要： The clock input of a buck converter is delayed, and the delay is controlled proportionally to the preceding high-side output switch on time. In the steady state, the high-side switch on time is uniform, and the clock is offset by a fixed amount. When sub-harmonic oscillation begins to occur, the high-side switch on time may increase during a cycle. The longer high-side on time causes the clock to be delayed by an increased amount. This has the effect of increasing the following low-side output switch on time. This further increases the subsequent high-side on time, and counteracts the effects of sub-harmonic oscillation. If the system is properly controlled, loop compensation is implemented correctly and sub-harmonic oscillation is prevented. In addition, the scheme may also be configured for the delay to be controlled proportionally to the preceding low-side output switch on time of the buck converter.
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公开(公告)号：US10044266B2
公开(公告)日：2018-08-07
申请号：US15701946
申请日：2017-09-12
发明人： Mark Childs , Michele DeFazio , Carsten Barth
摘要： The proposed disclosure combines peak-mode monitoring with valley-mode control, in a Buck switching converter, by means of a peak-current sampling circuit, not to turn the high side device off, but to control a slow loop, which in turn controls a variable offset incorporated into the loop control current. This helps the loop control current define the exact peak current, regardless of what other offsets, compensation ramp or peak-to-peak current ripple, are applied to the loop control current. The peak current is determined by an operational transconductance amplifier (OTA), whose maximum current is clamped to a programmed value. The loop control current is most likely implemented using a digital successive approximation register (SAR) system, but may also be implemented using a slow analog control loop.
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公开(公告)号：US20170288548A1
公开(公告)日：2017-10-05
申请号：US15596399
申请日：2017-05-16
发明人： Mark Childs , Paul Collins
CPC分类号： H02M3/158 , H02M1/083 , H02M1/32 , H02M3/1588 , H02M2001/0009 , H02M2001/0032 , Y02B70/1466
摘要： A switching mode power supply (SMPS) configured for clearing an overvoltage condition. The overvoltage is determined by detecting that the output voltage has exceeded the input voltage by a limited amount. The overvoltage is cleared by repetitively turning on and then off the switches controlling the flow of energy to the SMPS in sequence until the excess charge resulting from the overvoltage is couple to circuit ground, and the output is reduced to within acceptable limits.
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公开(公告)号：US09742280B2
公开(公告)日：2017-08-22
申请号：US15175301
申请日：2016-06-07
发明人： Mark Childs , Jens Masuch
CPC分类号： H02M3/158 , H02M1/08 , H02M3/1584 , H02M2001/0009 , H02M2003/1586
摘要： In order to accelerate the response of buck converters to load transients buck converters having asymmetric phase designs having a load step detection are used. When a relatively large and fast load step is detected, the clock frequency of “fast”valley mode phases is reduced, which are populated with fast, low value inductors. The clock frequency is returned to its normal rate when the current in the “slow” phases has reached a suitable level.
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