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    DEEP TRENCH ISOLATION WITH FIELD OXIDE
    1.
    发明申请
    DEEP TRENCH ISOLATION WITH FIELD OXIDE 有权

    公开(公告)号：US20240429275A1

    公开(公告)日：2024-12-26

    申请号：US18776479

    申请日：2024-07-18

    Applicant: Texas Instruments Incorporated

    Inventor： Abbas Ali ,  Rajni J. Aggarwal ,  Steven J. Adler ,  Eugene C. Davis

    IPC: H01L29/06 ,  H01L21/265 ,  H01L21/761 ,  H01L21/762 ,  H01L21/763

    Abstract: An electronic device comprises a semiconductor substrate including majority carrier dopants of a first conductivity type, a semiconductor surface layer including majority carrier dopants of a second conductivity type, field oxide that extends on the semiconductor surface layer, and an isolation structure. The isolation structure includes a trench that extends through the semiconductor surface layer and into one of the semiconductor substrate and a buried layer of the semiconductor substrate, and polysilicon including majority carrier dopants of the second conductivity type, the polysilicon fills the trench to a side of the semiconductor surface layer.

    Integrated trench capacitor with top plate having reduced voids
    4.
    发明授权
    Integrated trench capacitor with top plate having reduced voids 有权

    公开(公告)号：US11121207B2

    公开(公告)日：2021-09-14

    申请号：US15348459

    申请日：2016-11-10

    Applicant: Texas Instruments Incorporated

    Inventor： Binghua Hu ,  Abbas Ali ,  Sopa Chevacharoenkul ,  Jarvis Benjamin Jacobs

    IPC: H01L49/02 ,  H01L21/762 ,  H01L21/265 ,  H01L21/308

    Abstract: A method for forming trench capacitors includes forming a silicon nitride layer over a first region of a semiconductor surface doped a first type and over a second region doped a second type. A patterned photoresist layer is directly formed on the silicon nitride layer. An etch forms a plurality of deep trenches (DTs) within the first region. A liner oxide is formed that lines the DTs. The silicon nitride layer is etched forming an opening through the silicon nitride layer that is at least as large in area as the area of an opening in the semiconductor surface of the DT below the silicon nitride layer. The liner oxide is removed, a dielectric layer(s) on a surface of the DTs is formed, a top plate material layer is deposited to fill the DTs, and the top plate material layer is removed beyond the DT to form a top plate.

    NOVEL SUBSTRATE CONTACT ETCH PROCESS
    6.
    发明申请
    NOVEL SUBSTRATE CONTACT ETCH PROCESS 审中-公开
    新型衬底接触蚀刻工艺

    公开(公告)号：US20170040426A1

    公开(公告)日：2017-02-09

    申请号：US15251443

    申请日：2016-08-30

    Applicant: Texas Instruments Incorporated

    Inventor： David William Hamann ,  Thomas E. Lillibridge ,  Abbas Ali

    IPC: H01L29/40 ,  H01L29/06

    CPC classification number: H01L29/408 ,  H01L21/0212 ,  H01L21/02274 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/743 ,  H01L29/0623 ,  H01L29/401 ,  H01L29/407

    Abstract: A semiconductor device with a deep trench has a dielectric liner formed on sidewalls and a bottom of the deep trench. A pre-etch deposition step of a two-step process forms a protective polymer on an existing top surface of the semiconductor device, and on the dielectric liner proximate to a top surface of the substrate. The pre-etch deposition step does not remove a significant amount of the dielectric liner from the bottom of the deep trench. A main etch step of the two-step process removes the dielectric liner at the bottom of the deep trench while maintaining the protective polymer at the top of the deep trench. The protective polymer is subsequently removed.

    Abstract translation: 具有深沟槽的半导体器件具有形成在深沟槽的侧壁和底部上的电介质衬垫。 两步法的预蚀刻沉积步骤在半导体器件的现有顶表面上以及靠近衬底顶表面的电介质衬垫上形成保护性聚合物。 预蚀刻沉积步骤不会从深沟槽的底部去除大量的电介质衬垫。 两步法的主蚀刻步骤除去深沟槽底部的电介质衬垫，同时将保护性聚合物保持在深沟槽的顶部。 随后除去保护性聚合物。

    Control of locos structure thickness without a mask
    8.
    发明授权
    Control of locos structure thickness without a mask 有权

    公开(公告)号：US11984362B1

    公开(公告)日：2024-05-14

    申请号：US17411761

    申请日：2021-08-25

    Applicant: Texas Instruments Incorporated

    Inventor： Abbas Ali ,  Christopher Scott Whitesell ,  John Christopher Shriner ,  Henry Litzmann Edwards

    IPC: H01L21/8234 ,  H01L27/088

    CPC classification number: H01L21/823462 ,  H01L27/088

    Abstract: A method of fabricating an integrated circuit includes forming a first opening having a first width and a second opening having a second width in a first dielectric layer over a silicon substrate. The openings expose the silicon substrate and the exposed silicon substrate is oxidized to form first and second LOCOS structures having a first thickness. A polysilicon layer is formed over the silicon substrate, so that the polysilicon layer fills the first and second openings. A blanket etch of the polysilicon layer is performed to remove at least a portion of the polysilicon layer over the second LOCOS structure while leaving the first LOCOS structure protected by the polysilicon layer. The silicon substrate under the second LOCOS structure is further oxidized such that the second LOCOS structure has a second thickness greater than the first thickness.

    Method of fabricating transistors, including ambient oxidizing after etchings into barrier layers and anti-reflecting coatings
    10.
    发明授权
    Method of fabricating transistors, including ambient oxidizing after etchings into barrier layers and anti-reflecting coatings 有权

    公开(公告)号：US10566200B2

    公开(公告)日：2020-02-18

    申请号：US15944550

    申请日：2018-04-03

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Abbas Ali ,  Binghua Hu ,  Stephanie L. Hilbun ,  Scott William Jessen ,  Ronald Chin ,  Jarvis Benjamin Jacobs

    IPC: H01L21/266 ,  H01L29/66

    Abstract: A method to fabricate a transistor comprises: forming a first dielectric layer on a semiconductor substrate; depositing a barrier layer on the first dielectric layer; depositing an anti-reflective coating on the barrier layer; depositing and exposing a pattern in a photoresist layer to radiation followed by etching to provide an opening; etching a portion of the anti-reflective coating below the opening; etching a portion of the barrier layer below the opening to expose a portion of the first dielectric layer; providing an ambient oxidizing agent to grow an oxide region followed by removing the barrier layer; implanting dopants into the semiconductor substrate after removing the barrier layer; removing the first dielectric layer after implanting dopants into the semiconductor substrate; and forming a second dielectric layer after removing the first dielectric layer, wherein the oxide region is grown to be thicker than the second dielectric layer.

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