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公开(公告)号：US09431064B2
公开(公告)日：2016-08-30
申请号：US13667924
申请日：2012-11-02
Inventor： Hsien-Hsin Sean Lee , William Wu Shen , Yun-Han Lee
CPC classification number: G06F12/0804 , G06F12/0891 , G06F2212/1008 , G06F2212/1032 , G06F2212/45 , G06F2212/608 , G11C5/025 , G11C5/04 , G11C7/22
Abstract: A cache memory die includes a substrate, a predetermined number of sets of memory cells on the substrate, a first set of input/output terminals on a first surface of the cache memory die, and a second set of input/output terminals on a second surface of the cache memory die. The first set of input/output terminals are connected to a primary memory circuit outside the cache memory die. A portion of the second set of input/output terminals are compatible with the first set of input/output terminals.
Abstract translation: 高速缓冲存储器管芯包括衬底，衬底上的预定数量的存储器单元组，高速缓冲存储器管芯的第一表面上的第一组输入/输出端子和第二组输入/输出端子 缓冲存储器表面死亡。 第一组输入/输出端子连接到高速缓冲存储器管芯外部的主存储器电路。 第二组输入/输出端子的一部分与第一组输入/输出端子兼容。
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公开(公告)号：US09158324B2
公开(公告)日：2015-10-13
申请号：US14025171
申请日：2013-09-12
Inventor： Shyh-An Chi , Shiue Tsong Shen , Jyy Anne Lee , Yun-Han Lee
IPC: G05F3/08 , H03K17/14 , G05F3/20 , H03K19/003
CPC classification number: G05F3/205 , H03K19/00384
Abstract: An integrated circuit includes a process voltage temperature (PVT) effect transducer responsive to a PVT effect, a PVT effect quantifier coupled to the PVT effect transducer and configured to quantify the PVT effect to provide an output, and a bias controller configured to receive the output of the PVT effect quantifier and provide a bias voltage for a substrate of an NMOS or a PMOS transistor. The bias controller is configured to compare the output received from the PVT effect quantifier to a threshold value, and decrease or increase the bias voltage depending on whether the output is higher or lower than the threshold value.
Abstract translation: 集成电路包括响应于PVT效应的过程电压温度（PVT）效应传感器，耦合到PVT效应传感器并被配置为量化PVT效应以提供输出的PVT效应量化器，以及配置成接收输出的偏置控制器 的PVT效应量化器，并为NMOS或PMOS晶体管的衬底提供偏置电压。 偏置控制器被配置为将从PVT效应量化器接收的输出与阈值进行比较，并且根据输出是高于还是低于阈值来降低或增加偏置电压。
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公开(公告)号：US12014130B2
公开(公告)日：2024-06-18
申请号：US17115407
申请日：2020-12-08
Inventor： Kai-Yuan Ting , Sandeep Kumar Goel , Tze-Chiang Huang , Yun-Han Lee
Abstract: A method includes receiving a source code for executing a plurality of operations associated with a machine learning algorithm, classifying each operation into a fast operation group and/or a slow operation group, defining a neuron network for executing operations of the slow operation group, and mapping the neuron network to an initial machine learning hardware configuration. The method also includes executing the slow operation group operation on the machine learning hardware configuration, finalizing the machine learning hardware configuration capable of successfully executing least one test data set.
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公开(公告)号：US20240120315A1
公开(公告)日：2024-04-11
申请号：US18169579
申请日：2023-02-15
Inventor： Ming-Fa Chen , Tze-Chiang Huang , Yun-Han Lee , Lee-Chung Lu
IPC: H01L25/065 , H01L23/00 , H01L23/31 , H01L23/48 , H01L23/538 , H01L25/00 , H01L25/18 , H10B80/00
CPC classification number: H01L25/0652 , H01L23/3185 , H01L23/481 , H01L23/538 , H01L23/5384 , H01L24/05 , H01L24/06 , H01L24/08 , H01L25/18 , H01L25/50 , H10B80/00 , H01L24/13 , H01L2224/0401 , H01L2224/0557 , H01L2224/05571 , H01L2224/05624 , H01L2224/05647 , H01L2224/05666 , H01L2224/05684 , H01L2224/06181 , H01L2224/08147 , H01L2224/08221 , H01L2224/13111 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13164
Abstract: A semiconductor package includes a first semiconductor die and a second semiconductor die disposed laterally adjacent one another. The semiconductor package includes a semiconductor bridge overlapping a first corner of the first semiconductor die and a second corner of the second semiconductor die. The semiconductor bridge electrically couples the first semiconductor to the second semiconductor die. The semiconductor package includes a third semiconductor die and a fourth semiconductor die electrically coupled to the first semiconductor die and the second semiconductor die, respectively. The semiconductor bridge is interposed between the third semiconductor die and the fourth semiconductor die.
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公开(公告)号：US11949603B2
公开(公告)日：2024-04-02
申请号：US18048863
申请日：2022-10-24
Inventor： Ravi Venugopalan , Sandeep Kumar Goel , Yun-Han Lee
IPC: H04L49/109 , H04L45/00 , H04L45/28
CPC classification number: H04L49/109 , H04L45/22 , H04L45/28
Abstract: A network-on-chip (NoC) system includes a default communication path between a master device and a slave device, and a backup communication path between the master device and the slave device. The default communication path is configured to work in a normal operation state of the chip. The backup communication path is configured to replace the default communication path when a fault arises in the default communication path.
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Patent Agency Ranking
公开(公告)号：US11854943B2
公开(公告)日：2023-12-26
申请号：US18153475
申请日：2023-01-12
Inventor： Hidehiro Fujiwara , Tze-Chiang Huang , Hong-Chen Cheng , Yen-Huei Chen , Hung-Jen Liao , Jonathan Tsung-Yung Chang , Yun-Han Lee , Lee-Chung Lu
IPC: G11C16/04 , H01L23/48 , H10B10/00 , G11C11/418 , H01L21/768
CPC classification number: H01L23/481 , G11C11/418 , H01L21/76898 , H10B10/18
Abstract: An integrated circuit (IC) package includes a logic die, a substrate, a memory die positioned between the logic die and the substrate, and a power distribution structure configured to electrically couple the logic die to the substrate. The power distribution structure includes a plurality of conductive segments positioned between the logic die and the memory die, a plurality of bump structures positioned between the memory die and the substrate, and a plurality of through-silicon vias (TSVs) electrically coupled to the plurality of conductive segments and the plurality of bump structures, and a TSV of the plurality of TSVs extends through, and is electrically isolated from, a memory macro of the memory die.
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公开(公告)号：US10685157B2
公开(公告)日：2020-06-16
申请号：US16135804
申请日：2018-09-19
Inventor： Ankita Patidar , Sandeep Kumar Goel , Yun-Han Lee
IPC: G06F30/333 , G01R31/3185 , G01R31/317 , G06F30/00
Abstract: Methods of a scan partitioning a circuit are disclosed. One method includes calculating a power score for circuit cells within a circuit design based on physical cell parameters of the circuit cells. For each of the circuit cells, the circuit cell is assigned to a scan group according to the power score for the circuit cell and a total power score for each scan group. A plurality of scan chains is formed. Each of the scan chains is formed from the circuit cells in a corresponding scan group based at least in part on placement data within the circuit design for each of the circuit cells. Interconnect power consumption can be assessed to determine routing among circuit cells in the scan chains.
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公开(公告)号：US10666578B2
公开(公告)日：2020-05-26
申请号：US15257210
申请日：2016-09-06
Inventor： Ravi Venugopalan , Sandeep Kumar Goel , Yun-Han Lee
IPC: H04L12/933 , H04L12/707 , H04L12/703
Abstract: A network-on-chip (NoC) system includes a default communication path between a master device and a slave device, and a backup communication path between the master device and the slave device. The default communication path is configured to work in a normal operation state of the chip. The backup communication path is configured to replace the default communication path when a fault arises in the default communication path.
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公开(公告)号：US10440281B2
公开(公告)日：2019-10-08
申请号：US14458815
申请日：2014-08-13
Inventor： Sandeep Kumar Goel , Yun-Han Lee , Ashok Mehta
Abstract: An apparatus comprises an integrated circuit and at least one lens. The integrated circuit comprises an image sensor having a light sensing region. The light sensing region is partitioned into sub-regions. The integrated circuit also comprises a processor coupled with and beneath the image sensor. The processor is configured to generate a first processed image based on an image captured by one sub-region, and a second processed image based on another image captured by another sub-region. The first processed image and the second processed image are generated based on a pixel correction process executed by the processor which corrects one or more of the image or the another image based on a predefined light reception factor associated with the sub-regions. The image sensor is configured to receive light via the light sensing region through the at least one lens.
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公开(公告)号：US09887863B2
公开(公告)日：2018-02-06
申请号：US14885352
申请日：2015-10-16
Inventor： Huan-Neng Chen , William Wu Shen , Lan-Chou Cho , Feng Wei Kuo , Chewn-Pu Jou , Tze-Chiang Huang , Jack Liu , Yun-Han Lee
CPC classification number: H04L27/0002 , H04B1/40 , H04B1/48 , H04B10/40 , H04L5/06 , H04L27/365 , H04L27/38 , H04L2027/0022
Abstract: A transceiver group includes a plurality of transceivers; wherein the transceiver group performs transmission and receiving through a wire, and each of the transceivers includes a transmitter and a receiver, and the transmitter includes: a carrier generator arranged to generate a plurality of carriers having different frequencies for a plurality of data streams to be transmitted; a modulator, coupled to the data streams to be transmitted and the carrier generator, to generate a plurality of modulated data streams carried on the plurality of carriers; and a summer arranged to merge the plurality of modulated data streams to an output signal to the wire; and the receiver includes: a carrier generator arranged to generate a plurality of carriers having different frequencies for an input signal received from the wire; and a demodulator, coupled to the input signal and the carrier generator, to generate a plurality of demodulated data streams.
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