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公开(公告)号：US20230377666A1
公开(公告)日：2023-11-23
申请号：US18362223
申请日：2023-07-31
Inventor： Meng-Sheng Chang , Chia-En Huang , Yih Wang
CPC classification number: G11C17/165 , H10B20/20
Abstract: A memory device is disclosed. The memory device includes a plurality of memory cells, each of the memory cells including an access transistor and a resistor coupled to each other in series. The resistors of the memory cells are each formed as one of a plurality of interconnect structures disposed over a substrate. The access transistors of the memory cells are disposed opposite a first metallization layer containing the plurality of interconnect structures from the substrate.
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公开(公告)号：US11791005B2
公开(公告)日：2023-10-17
申请号：US17154576
申请日：2021-01-21
Inventor： Meng-Sheng Chang , Chia-En Huang , Yih Wang
Abstract: A memory circuit includes a first programming device, a first circuit branch and a second circuit branch. The first programming device includes a first control terminal coupled to a first word line, and a first connecting end. The first circuit branch includes a first diode, and a first fuse element coupled to the first diode. The second circuit branch includes a second diode, and a second fuse element coupled to the second diode. The first circuit branch and the second circuit branch are coupled to the first connecting end of the first programming device.
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公开(公告)号：US11776595B2
公开(公告)日：2023-10-03
申请号：US17584127
申请日：2022-01-25
Inventor： Perng-Fei Yuh , Yih Wang
CPC classification number: G11C7/1096 , G11C7/1069 , G11C7/12 , G11C8/08 , G11C11/165 , G11C11/407 , G11C17/18
Abstract: Disclosed herein are related to a memory device including a set of memory cells and a memory controller. In one aspect, each of the set of memory cells includes a select transistor and a storage element connected in series between a corresponding bit line and a corresponding source line. In one aspect, the memory controller is configured to apply a first write voltage to a bit line coupled to a selected memory cell, apply a second write voltage to a word line coupled to a gate electrode of a select transistor of the selected memory cell during a first time period, and apply a third write voltage to a source line coupled to the selected memory cell. The second write voltage may be between the first write voltage and the third write voltage.
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公开(公告)号：US11770934B2
公开(公告)日：2023-09-26
申请号：US17400087
申请日：2021-08-11
Inventor： Bo-Feng Young , Sai-Hooi Yeong , Shih-Lien Linus Lu , Chia-En Huang , Yih Wang , Yu-Ming Lin
IPC: G11C11/22 , H10B51/20 , G11C5/06 , H01L23/522
CPC classification number: H10B51/20 , G11C5/06 , G11C11/223 , H01L23/5221
Abstract: A semiconductor structure includes a memory array, a staircase unit, conductive bridge structures, a word line driver and conductive routings. The memory array is disposed in an array region of the semiconductor structure and includes word lines. The staircase unit is disposed in a staircase region and surrounded by the array region. The staircase unit includes first and second staircase steps extending from the word lines of the memory array. The first staircase steps and the second staircase steps face towards each other. The conductive bridge structures are electrically connecting the first staircase steps to the second staircase step. The word line driver is disposed below the memory array and the staircase unit, wherein a central portion of the word line driver is overlapped with a central portion of the staircase unit. The conductive routings extend from the first and the second staircase steps to the word line driver.
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公开(公告)号：US11758715B2
公开(公告)日：2023-09-12
申请号：US17876103
申请日：2022-07-28
Inventor： Meng-Sheng Chang , Chia-En Huang , Shao-Yu Chou , Yih Wang
IPC: H10B20/20 , H01L23/528 , H01L23/532 , G11C17/16 , G06F30/392 , H01L23/525 , G11C17/18
CPC classification number: H10B20/20 , G06F30/392 , G11C17/16 , G11C17/18 , H01L23/528 , H01L23/5252 , H01L23/53271
Abstract: A memory device includes a first memory cell having a first polysilicon line associated with a first read word line and intersecting a first active region and a second active region, and a second polysilicon line and a first CPODE associated with a first program word line, the second polysilicon line intersecting the first active region and the first CPODE intersecting the second active region. The memory device also includes a second memory cell adjacent to the first memory cell, the second memory cell having a third polysilicon line associated with a second read word line and intersecting the first active region and the second active region, and a fourth polysilicon line and a second CPODE associated with a second program word line, the fourth polysilicon line intersecting the second active region and the second CPODE intersecting the first active region to form a cross-arrangement of CPODE.
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Patent Agency Ranking
公开(公告)号：US11756591B2
公开(公告)日：2023-09-12
申请号：US17460215
申请日：2021-08-28
Inventor： Meng-Sheng Chang , Chia-En Huang , Yi-Ching Liu , Yih Wang
IPC: G11C5/06
CPC classification number: G11C5/063
Abstract: Disclosed herein are related to a memory array including a set of memory cells and a set of switches to configure the set of memory cells. In one aspect, each switch is connected between a corresponding local line and a corresponding subset of memory cells. The local clines may be connected to a global line. Local lines may be metal rails, for example, local bit lines or local select lines. A global line may be a metal rail, for example, a global bit line or a global select line. A switch may be enabled or disabled to electrically couple a controller to a selected subset of memory cells through the global line. Accordingly, the set of memory cells can be configured through the global line rather than a number of metal rails to achieve area efficiency.
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公开(公告)号：US11742021B2
公开(公告)日：2023-08-29
申请号：US17815076
申请日：2022-07-26
Inventor： Hiroki Noguchi , Yu-Der Chih , Yih Wang
CPC classification number: G11C13/0069 , G11C11/1675 , G11C11/2275 , G11C2013/0092
Abstract: A memory device includes: a memory cell array comprising a plurality of memory cells; a temperature sensor configured to detect a temperature of the memory cell array; a write circuit configured to write data into the plurality of memory cells; and a controller coupled to the temperature sensor and the write circuit, wherein the controller is configured to determine a target write pulse width used by the write circuit based on the detected temperature of the memory device.
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公开(公告)号：US11714570B2
公开(公告)日：2023-08-01
申请号：US17130918
申请日：2020-12-22
Inventor： Jonathan Tsung-Yung Chang , Hidehiro Fujiwara , Hung-Jen Liao , Yen-Huei Chen , Yih Wang , Haruki Mori
IPC: G06F3/06 , G11C11/419 , G11C7/10 , G11C8/16 , G06N3/063
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0673 , G06N3/063 , G11C7/10 , G11C8/16 , G11C11/419
Abstract: A charge sharing scheme is used to mitigate the variations in cell currents in order to achieve higher accuracy for CIM computing. In some embodiments, a capacitor is associated with each SRAM cell, and the capacitors associated with all SRAM cells in a column are included in averaging the RBL current. In some embodiments, a memory unit associated to an RBL in a CIM device includes a storage element adapted to store a weight, a first switch device connected to the storage element and adapted to be controlled by an input signal and generate a product signal having a magnitude indicative of the product of the input signal and the stored weight. The memory unit further includes a capacitor adapted to receive the product signal and store an amount of charge corresponding to the magnitude of the product signal. The memory unit further include a second switch device adapted to transfer the charge on the capacitor to the RBL.
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公开(公告)号：US11688481B2
公开(公告)日：2023-06-27
申请号：US17484730
申请日：2021-09-24
Inventor： Perng-Fei Yuh , Tung-Cheng Chang , Gu-Huan Li , Chia-En Huang , Jimmy Lee , Yih Wang
Abstract: A memory device and a method of operating a memory device are disclosed. In one aspect, the memory device includes a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells is operatively coupled to a word line, a gate control line, and a bit line. Each of the plurality of non-volatile memory cells comprises a first transistor, a second transistor, a first diode-connected transistor, and a capacitor. The first transistor, second transistor, first diode-connected transistor are coupled in series, with the capacitor having a first terminal connected to a common node between the first diode-connected transistor and the second transistor.
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公开(公告)号：US11682433B2
公开(公告)日：2023-06-20
申请号：US17460938
申请日：2021-08-30
Inventor： Perng-Fei Yuh , Meng-Sheng Chang , Tung-Cheng Chang , Yih Wang
CPC classification number: G11C5/147 , G11C7/1084 , G11C17/165 , G11C17/18
Abstract: One aspect of this description relates to a memory array. The memory array includes a plurality of N-stack pass gates, a plurality of enable lines, a plurality of NMOS stacks, a plurality of word lines, and a matrix of resistive elements. Each N-stack pass gate includes a stage-1 PMOS core device and a stage-N PMOS core device in series. Each stage-1 PMOS is coupled to a voltage supply. Each enable line drives a stack pass gate. Each N-stack selector includes a plurality of NMOS stacks. Each NMOS stack includes a stage-1 NMOS core device and a stage-N N MOS core device in series. Each stage-1 NMOS core device is coupled to a ground rail. Each word line is driving a stack selector. Each resistive element is coupled between a stack pass gate and a stack selector. Each voltage supply is greater than a breakdown voltage for each of the core devices.
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