公开(公告)号：US20150179795A1

公开(公告)日：2015-06-25

申请号：US14626211

申请日：2015-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong Hyuk KIM ,  Hoi Sung Chung ,  Dongsuk Shin ,  Naein Lee

IPC: H01L29/78 ,  H01L29/04

CPC classification number: H01L29/7833 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66477 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device including source drain stressors and methods of manufacturing the same are provided. The methods may include forming a recess region in the substrate at a side of a gate pattern, and an inner surface of the recess region may include a first surface of a (100) crystal plane and a second surface of one of {111} crystal planes. The method may further include performing a first selective epitaxial growth (SEG) process to form a base epitaxial pattern on the inner surface of the recess region at a process pressure in a range of about 50 Torr to about 300 Torr. The method may also include performing a second selective epitaxial growth (SEG) process to form a bulk epitaxial pattern on the base epitaxial pattern.

Abstract translation: 提供了包括源漏应力源的半导体器件及其制造方法。 所述方法可以包括在栅极图案侧的基板中形成凹陷区域，并且凹部区域的内表面可以包括（100）晶面的第一表面和{111}晶体之一的第二表面 飞机 该方法还可以包括执行第一选择性外延生长（SEG）工艺，以在约50托至约300托的范围内的工艺压力下在凹陷区的内表面上形成基底外延图案。 该方法还可以包括执行第二选择性外延生长（SEG）工艺以在基底外延图案上形成体外延图案。

公开(公告)号：US09911644B2

公开(公告)日：2018-03-06

申请号：US15359724

申请日：2016-11-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wookyung You ,  Jongmin Baek ,  Sanghoon Ahn ,  Sangho Rha ,  Naein Lee

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02208 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02345 ,  H01L21/02348 ,  H01L21/311 ,  H01L21/31144 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure describes semiconductor devices and methods of fabricating the same. The method includes forming an interlayer insulating layer on a substrate and forming conductive patterns in the interlayer insulating layer. A pore density of an upper portion of the interlayer insulating layer is higher than that of a lower portion of the interlayer insulating layer, and a pore density of an intermediate portion of the interlayer insulating layer gradually increases toward the upper portion of the interlayer insulating layer. An air gap is provided between the conductive patterns.

公开(公告)号：US09548389B2

公开(公告)日：2017-01-17

申请号：US14969702

申请日：2015-12-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghyun Roh ,  Pankwi Park ,  Dongsuk Shin ,  Chulwoong Lee ,  Naein Lee

IPC: H01L27/092 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/161 ,  H01L29/165

CPC classification number: H01L29/7849 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/66477 ,  H01L29/66553 ,  H01L29/7848

Abstract: According to embodiments of the inventive concept, a gate electrode is formed on a substrate, and a first spacer, a second spacer, and a third spacer are sequentially formed on a sidewall of the gate electrode. The substrate is etched to form a recess region. A compressive stress pattern is formed in the recess region. A protective spacer is formed on a sidewall of the third spacer. When the recess region is formed, a lower portion of the second spacer is removed to form a gap region between the first and third spacers. The protective spacer fills the gap region.

Abstract translation: 根据本发明构思的实施例，栅极形成在衬底上，并且第一间隔物，第二间隔物和第三间隔物依次形成在栅电极的侧壁上。 蚀刻衬底以形成凹陷区域。 在凹部形成压缩应力图形。 在第三间隔件的侧壁上形成保护隔离件。 当形成凹陷区域时，去除第二间隔物的下部以在第一和第三间隔物之间​​形成间隙区域。 保护性间隔物填充间隙区域。

公开(公告)号：US09520300B2

公开(公告)日：2016-12-13

申请号：US14606970

申请日：2015-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wookyung You ,  Jongmin Baek ,  Sanghoon Ahn ,  Sangho Rha ,  Naein Lee

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02208 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02345 ,  H01L21/02348 ,  H01L21/311 ,  H01L21/31144 ,  H01L21/76834 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure describes semiconductor devices and methods of fabricating the same. The method includes forming an interlayer insulating layer on a substrate and forming conductive patterns in the interlayer insulating layer. A pore density of an upper portion of the interlayer insulating layer is higher than that of a lower portion of the interlayer insulating layer, and a pore density of an intermediate portion of the interlayer insulating layer gradually increases toward the upper portion of the interlayer insulating layer. An air gap is provided between the conductive patterns.

Abstract translation: 本公开描述了半导体器件及其制造方法。 该方法包括在衬底上形成层间绝缘层，并在层间绝缘层中形成导电图案。 层间绝缘层的上部的孔密度高于层间绝缘层的下部的孔密度，层间绝缘层的中间部分的孔密度朝向层间绝缘层的上部逐渐增加 。 在导电图案之间设置气隙。

公开(公告)号：US09312171B2

公开(公告)日：2016-04-12

申请号：US14490964

申请日：2014-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Hee Han ,  Pil-Kyu Kang ,  Taejin Yim ,  Naein Lee

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76879 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present inventive concepts provide semiconductor devices and methods for fabricating the same. The method includes forming an inter-metal dielectric layer including a plurality of dielectric layers on a substrate, forming a via-hole vertically penetrating the inter-metal dielectric layer and the substrate, providing carbon to at least one surface, such as a surface including carbon in the plurality of dielectric layers exposed by the via-hole, forming a via-dielectric layer covering an inner surface of the via-hole, and forming a through-electrode surrounded by the via-dielectric layer in the via-hole.

Abstract translation: 本发明构思提供半导体器件及其制造方法。 该方法包括在基板上形成包括多个电介质层的金属间介电层，形成垂直贯穿金属间介电层和基板的通孔，向至少一个表面提供碳，例如包括 通过通孔露出的多个电介质层中的碳，形成覆盖通路孔的内表面的通孔电介质层，以及形成由通路孔中的通孔电介质层包围的贯通电极。

公开(公告)号：US20150187699A1

公开(公告)日：2015-07-02

申请号：US14503877

申请日：2014-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongmin Baek ,  Sangho Rha ,  Sanghoon Ahn ,  Wookyung You ,  Naein Lee

IPC: H01L23/528 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L21/7682 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices are provided. A semiconductor device includes gaps between conductive patterns. Moreover, the semiconductor device includes a permeable layer on the conductive patterns. Methods of fabricating semiconductor devices are also provided.

Abstract translation: 提供半导体器件。 半导体器件包括导电图案之间的间隙。 此外，半导体器件在导电图案上包括可渗透层。 还提供了制造半导体器件的方法。

公开(公告)号：US20140087535A1

公开(公告)日：2014-03-27

申请号：US13957912

申请日：2013-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghyun Roh ,  Pankwi Park ,  Dongsuk Shin ,  Chulwoong Lee ,  Naein Lee

IPC: H01L29/66

CPC classification number: H01L29/7849 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/66477 ,  H01L29/66553 ,  H01L29/7848

Abstract: According to embodiments of the inventive concept, a gate electrode is formed on a substrate, and a first spacer, a second spacer, and a third spacer are sequentially formed on a sidewall of the gate electrode. The substrate is etched to form a recess region. A compressive stress pattern is formed in the recess region. A protective spacer is formed on a sidewall of the third spacer. When the recess region is formed, a lower portion of the second spacer is removed to form a gap region between the first and third spacers. The protective spacer fills the gap region.

Abstract translation: 根据本发明构思的实施例，栅极形成在衬底上，并且第一间隔物，第二间隔物和第三间隔物依次形成在栅电极的侧壁上。 蚀刻衬底以形成凹陷区域。 在凹部形成压缩应力图形。 在第三间隔件的侧壁上形成保护隔离件。 当形成凹陷区域时，去除第二间隔物的下部，以在第一和第三间隔物之间​​形成间隙区域。 保护性间隔物填充间隙区域。

公开(公告)号：US10438802B2

公开(公告)日：2019-10-08

申请号：US15679315

申请日：2017-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun Park ,  Naein Lee

IPC: H01L21/285 ,  H01L21/28 ,  H01L21/311 ,  H01L21/32 ,  H01L21/3205 ,  H01L27/108 ,  H01L29/51 ,  H01L27/11582

Abstract: A method of fabricating a semiconductor device, the method including forming a deposition active layer and a guide pattern on a semiconductor substrate such that the guide pattern delimits an exposed surface of the deposition active layer; and selectively depositing a metal-containing layer on the exposed surface of the deposition active layer exposed by the guide pattern, wherein the deposition active layer is a nonmetal layer.

公开(公告)号：US10199325B2

公开(公告)日：2019-02-05

申请号：US15792911

申请日：2017-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejin Yim ,  Jongmin Baek ,  Deokyoung Jung ,  Kyuhee Han ,  Byunghee Kim ,  Jiyoung Kim ,  Naein Lee ,  Sangshin Jang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: A semiconductor device is provided. The semiconductor device includes first metal lines on a lower layer, a dielectric barrier layer provided on the lower layer to cover side and top surfaces of the first metal lines, an etch stop layer provided on the dielectric barrier layer to define gap regions between the first metal lines, an upper insulating layer on the etch stop layer, and a conductive via penetrating the upper insulating layer, the etch stop layer, and the dielectric barrier layer to contact a top surface of a first metal line. The etch stop layer includes first portions on the first metal lines and second portions between the first metal lines. The second portions of the etch stop layer are higher than the first portions.

公开(公告)号：US10186485B2

公开(公告)日：2019-01-22

申请号：US15897465

申请日：2018-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： VietHa Nguyen ,  Wookyung You ,  Inoue Naoya ,  Hak-Sun Lee ,  Byung-Kwon Cho ,  Songyi Han ,  Jongmin Baek ,  Jiwon Kang ,  Byunghee Kim ,  Young-Ju Park ,  Sanghoon Ahn ,  Jiwon Yun ,  Naein Lee ,  YoungWoo Cho

IPC: H01L23/48 ,  H01L23/532 ,  H01L23/522

Abstract: A semiconductor device includes an interlayer insulating layer including a first insulating layer on a substrate, and a plurality of interconnections in the first insulating layer. The interlayer insulating layer includes a first region, and a second region including an air gap. The air gap is defined between a pair of the interconnections in the second region. A top surface of the first insulating layer of the first region is lower than a top surface of at least one of the interconnections in the first region.